Close the fpga_gate and asic_gate: core/vm timing, dxa drain, baseline refresh

[tinebp]

This branch makes both synthesis gates pass on every DUT. Each commit fixes one root cause, and none of them moves a cycle count.

Gate	Result	Before
fpga_gate (xcu55c)	12/12 PASS	core and vm failed their Fmax floor, top failed its LUT cap, tensor was STALE
asic_gate (Yosys/OpenSTA, ASAP7)	8/8 PASS	dxa over its area limit and STALE

Commits

Commit	Area	Fix	Measured
fe67ae44b	config	The LMEM floor now holds a full warp-count CTA group. At 8 KiB, an NT=4 core fit only three of the four co-resident CTAs that sgemm2_dxa_mcast waits on, so SimX and RTL both hung.	rtlsim matches the recorded baseline; model_parity 29/29
26f4882d6	dxa	The LMEM drain is back to one element per beat. The word-granular gather cost ~6.9k LUT of mux fabric on an unpipelinable path.	Xilinx 249 → 305 MHz, LUT +41.6% → +2%; ASAP7 cells +14% → +2%. Costs ~18% on DXA-fed WGMMA shapes
727b8710b	ci	Re-records the asic_gate dxa baseline, which was the last one left on the old Yosys/OpenSTA toolchain.	STALE → PASS
a7888b314	core	Takes the issue arbiter out of the scoreboard hazard loop and narrows the stack AGU. The NT16 dispatch queue and LSU request queue get a default-off, FPGA-only BRAM hint.	core 272.8 → 285.2 MHz
87beeb8b6	cache, vm	L2 AMO engine: registered look-ahead lane hits; coalesce computed for both drain outcomes; settling entry kept disjoint so the forward merge is an OR-tree; response reuses the bank's forwarded word. TLB: per-entry permission check. dmmu output pipe: new opt-in LATE_VALID skid mode in VX_stream_buffer. L2 fill crossbar: OUT_BUF 2.	vm 234.2 → 250.4 MHz, LUT −12.4%; top LUT +5.4% → +4.5%; cache LUT −5.8%
d5a47950e	core	CSR decode and read-modify-write run in the one-cycle wait every CSR request already takes (for the CTA RAM). Only values that can still move are read at fire, and trap-CSR writes use a one-hot target. Also fixes two latent bugs: CSR writes now happen on fire (a full response buffer made CSRRW return the new value), and VX_dcr_data latches the MPM class with its address.	core 268.5 → 286 MHz; SFU lane dispatch about −300 LUT/core
428d65c11	fpu	At LATENCY 5, fcvt counts leading zeros on ~x for a negative integer, plus a power-of-two correction, instead of waiting on the negate.	Dispatcher → fcvt path; identity checked exhaustively over int32
248fb33b6	ci	Records the improved cache and vm synthesis baselines.	—
feb8965ef	ci	Re-records tensor. Pinning its impl_strategy (ebc67f7a9, ce9bb0c55) changed its config hash without a refresh, so it had read STALE since 08-28.	STALE → PASS; within tolerance of the old numbers

Verification

• fpga_gate: full 12-DUT run on the final tree, all PASS:

  DUT	Fmax (MHz)	LUT
  core	286	179,058
  vm	250.4	119,695
  top	253	133,027 (+4.5%)
  cache	302	28,369
  tensor	250.5	239,260
  gfx, tcu, tex, rtu, dxa, raster, om	unchanged	unchanged

• asic_gate: full 8-DUT run, all PASS, every DUT within ±1% of its baseline.

• rtlsim, cycle- and instruction-identical to pre-change runs:

  • core: 34/34 perf lines.
  • amo + vm: 31/31 passing.
  • riscv ISA: 11/11 passing, including isa-32f-dsp, the only config that exercises the RTL fcvt. The default rtlsim FPU is DPI.

• New SIMULATION assertions: each new registered or look-ahead path is checked against the logic it replaces. Each check was confirmed to fire on a known-bad mutation of its own path:

  • CSR capture
  • AMO registered hits and settling-entry disjointness
  • AMO in-place old value
  • fcvt LZC

• Libraries: the VX_stream_buffer LATE_VALID mode is off by default. It matched the accept-enabled form over 4M random cycles, and a known-bad variant fails.

• No SimX change: no cycle count moved. That is covered by the rtlsim identity above, plus model_parity for the config and core commits.

Known, not addressed here

• Stale perf baselines: 16 core rtlsim cases fail perf_gate only because their perf-baseline config hashes are stale. The failing set is identical before and after this branch, and regenerating them is a separate reviewed step. The three WGMMA+DXA perf baselines (see 26f4882d6) are in the same state.
• Thin margins: core is 2.8 MHz above its 283.2 MHz floor, and top is 0.5% under its LUT cap.
• Trap-CSR ordering race: csrw mepc; mret and csrw mtvec; ecall are not ordered, because CSR ops are not wstall. No current test reaches it, including the rv32ui-p startup, which does exactly csrw mepc; mret. It needs a directed test and a matching SimX decode change.
• asic_gate toolchain path: build32_asic_gate must be run with TOOLDIR=~/tools; its configured TOOLDIR points at a path that no longer exists.

🤖 Generated with Claude Code