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Fix operand types in aarch64 inline asm #8

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Merged
guillerodriguez merged 1 commit into from
Feb 9, 2026
Merged

Fix operand types in aarch64 inline asm #8

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7 changes: 4 additions & 3 deletions src/arch/aarch64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,8 @@

#define COMPARE_AND_SWAP_64(addr, old_val, new_val) \
({ \
int result, read_val; \
int result; \
uintptr_t read_val; \
__asm__ __volatile__ (" \
1: ldaxr %2, %1\n \
cmp %2, %3\n \
Expand All @@ -46,7 +47,7 @@
b.ne 1b\n \
2: cset %w0, eq" \
: "=&r" (result), "+Q" (*addr), "=&r" (read_val) \
: "r" (old_val), "r" (new_val) \
: "r" ((uintptr_t)(old_val)), "r" ((uintptr_t)(new_val)) \
: "cc"); \
result; \
})
Expand Down Expand Up @@ -87,7 +88,7 @@
__asm__ __volatile__ (" \
stlr %1, %0" \
: "=Q" (*addr) \
: "r" (value) \
: "r" ((uintptr_t)(value)) \
: "cc"); \
})

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2 changes: 1 addition & 1 deletion src/os/linux/aarch64/init.c
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Expand Up @@ -36,7 +36,7 @@ unsigned char aarch64_instruction_cache_line_len;
uintptr_t aarch64_instruction_cache_line_mask;

void initialisePlatform() {
unsigned int cache_type;
unsigned long cache_type;

/* Extract information from the cache-type register, which describes aspects
of the host's cache configuration */
Expand Down