WIP: feat(esp32p4): enable PVT auto-dbias and run CPU at CPLL/1 (IDFGH-18044)

src/target/esp32p4/include/soc/hp_sys_clkrst_reg.h

@@ -57,3 +57,72 @@
 #define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_S)
 #define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_V  0x000000FFU
 #define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_S  16
+
+/** HP_SYS_CLKRST_SOC_CLK_CTRL1_REG register */
+#define HP_SYS_CLKRST_SOC_CLK_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x18)
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_S  25
+
+/** HP_SYS_CLKRST_REF_CLK_CTRL2_REG register */
+#define HP_SYS_CLKRST_REF_CLK_CTRL2_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x2c)
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_160M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_160M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL24_REG register */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL24_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa4)
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_S  16
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN_S  24
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL25_REG register */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL25_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa8)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_M                                                                    \
+    (HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_S  0
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_S  8
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_S  9
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_S  10
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_S  11
+
+/** HP_SYS_CLKRST_ANA_PLL_CTRL0_REG register */
+#define HP_SYS_CLKRST_ANA_PLL_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xbc)
+/** HP_SYS_CLKRST_REG_CPU_PLL_CAL_END : RO; bitpos: [2] */
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END    (BIT(2))
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_V << HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_S  2
+/** HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP : R/W; bitpos: [3] */
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP    (BIT(3))
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_V << HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_S  3
+
+/** HP_SYS_CLKRST_HP_RST_EN0_REG register */
+#define HP_SYS_CLKRST_HP_RST_EN0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc0)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4    (BIT(5))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_V << HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_S  5

src/target/esp32p4/include/soc/lp_i2c_ana_mst_reg.h

@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ *
+ * Minimal LP_I2C_ANA_MST defs for CPLL regi2c writes.
+ */
+
+#pragma once
+
+#include <esp-stub-lib/bit_utils.h>
+#include "reg_base.h"
+
+/** LP_I2C_ANA_MST_I2C0_CTRL_REG register */
+#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0)
+
+/** LP_I2C_ANA_MST_ANA_CONF1_REG register */
+#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x1c)
+#define LP_I2C_ANA_MST_ANA_CONF1    0x00FFFFFFU
+#define LP_I2C_ANA_MST_ANA_CONF1_M  (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S)
+#define LP_I2C_ANA_MST_ANA_CONF1_V  0x00FFFFFFU
+#define LP_I2C_ANA_MST_ANA_CONF1_S  0
+
+/** LP_I2C_ANA_MST_ANA_CONF2_REG register */
+#define LP_I2C_ANA_MST_ANA_CONF2_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x20)
+#define LP_I2C_ANA_MST_ANA_CONF2    0x00FFFFFFU
+#define LP_I2C_ANA_MST_ANA_CONF2_M  (LP_I2C_ANA_MST_ANA_CONF2_V << LP_I2C_ANA_MST_ANA_CONF2_S)
+#define LP_I2C_ANA_MST_ANA_CONF2_V  0x00FFFFFFU
+#define LP_I2C_ANA_MST_ANA_CONF2_S  0
+
+/** LP_I2C_ANA_MST_CLK160M_REG register */
+#define LP_I2C_ANA_MST_CLK160M_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x34)
+#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M    (BIT(0))
+#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M                                                                    \
+    (LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S)
+#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V  0x00000001U
+#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S  0

src/target/esp32p4/include/soc/lpperi_reg.h

@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ *
+ * Minimal LPPERI defs for analog I2C master clock gating (CPLL regi2c).
+ */
+
+#pragma once
+
+#include <esp-stub-lib/bit_utils.h>
+#include "reg_base.h"
+
+/** LPPERI_CLK_EN_REG register */
+#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
+/** LPPERI_CK_EN_LP_I2CMST : R/W; bitpos: [27]; default: 1 */
+#define LPPERI_CK_EN_LP_I2CMST    (BIT(27))
+#define LPPERI_CK_EN_LP_I2CMST_M  (LPPERI_CK_EN_LP_I2CMST_V << LPPERI_CK_EN_LP_I2CMST_S)
+#define LPPERI_CK_EN_LP_I2CMST_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2CMST_S  27

src/target/esp32p4/include/soc/pmu_reg.h

@@ -53,6 +53,11 @@
 
 /** PMU_HP_ACTIVE_HP_REGULATOR0_REG register */
 #define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28)
+/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4] */
+#define PMU_LP_DBIAS_VOL    0x0000001FU
+#define PMU_LP_DBIAS_VOL_M  (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S)
+#define PMU_LP_DBIAS_VOL_V  0x0000001FU
+#define PMU_LP_DBIAS_VOL_S  4
 /** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9] — PVT-sampled HP dbias/dcm hint */
 #define PMU_HP_DBIAS_VOL    0x0000001FU
 #define PMU_HP_DBIAS_VOL_M  (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S)
@@ -62,6 +67,10 @@
 #define PMU_DIG_REGULATOR0_DBIAS_SEL_M  (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S)
 #define PMU_DIG_REGULATOR0_DBIAS_SEL_V  0x00000001U
 #define PMU_DIG_REGULATOR0_DBIAS_SEL_S  14
+#define PMU_DIG_DBIAS_INIT    (BIT(15))
+#define PMU_DIG_DBIAS_INIT_M  (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S)
+#define PMU_DIG_DBIAS_INIT_V  0x00000001U
+#define PMU_DIG_DBIAS_INIT_S  15
 #define PMU_HP_ACTIVE_HP_REGULATOR_XPD    (BIT(18))
 #define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S)
 #define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V  0x00000001U
@@ -71,12 +80,17 @@
 #define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V  0x0000001FU
 #define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S  27
 
-/** PMU_LP_ACTIVE_LP_REGULATOR0_REG register (lp_sys[PMU_MODE_LP_ACTIVE]) */
+/** PMU_LP_ACTIVE_LP_REGULATOR0_REG / PMU_HP_SLEEP_LP_REGULATOR0_REG (same offset) */
 #define PMU_LP_ACTIVE_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c)
+#define PMU_HP_SLEEP_LP_REGULATOR0_REG  PMU_LP_ACTIVE_LP_REGULATOR0_REG
 #define PMU_LP_ACTIVE_LP_REGULATOR_DBIAS    0x0000001FU
 #define PMU_LP_ACTIVE_LP_REGULATOR_DBIAS_M  (PMU_LP_ACTIVE_LP_REGULATOR_DBIAS_V << PMU_LP_ACTIVE_LP_REGULATOR_DBIAS_S)
 #define PMU_LP_ACTIVE_LP_REGULATOR_DBIAS_V  0x0000001FU
 #define PMU_LP_ACTIVE_LP_REGULATOR_DBIAS_S  27
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS     PMU_LP_ACTIVE_LP_REGULATOR_DBIAS
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M   PMU_LP_ACTIVE_LP_REGULATOR_DBIAS_M
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V   PMU_LP_ACTIVE_LP_REGULATOR_DBIAS_V
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S   PMU_LP_ACTIVE_LP_REGULATOR_DBIAS_S
 
 /** PMU_IMM_HP_CK_POWER_REG register */
 #define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc)

src/target/esp32p4/include/soc/pvt_reg.h

@@ -0,0 +1,105 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ *
+ * Subset of PVT register definitions for stub auto-dbias init.
+ * See ESP-IDF components/soc/esp32p4/register/hw_ver3/soc/pvt_reg.h.
+ */
+
+#pragma once
+
+#include <bit_utils.h>
+#include "reg_base.h"
+
+#define PVT_CLK_CFG_REG (DR_REG_PVT_BASE + 0x30)
+#define PVT_MONITOR_CLK_PVT_EN    (BIT(8))
+#define PVT_MONITOR_CLK_PVT_EN_M  (PVT_MONITOR_CLK_PVT_EN_V << PVT_MONITOR_CLK_PVT_EN_S)
+#define PVT_MONITOR_CLK_PVT_EN_V  0x00000001U
+#define PVT_MONITOR_CLK_PVT_EN_S  8
+
+#define PVT_DBIAS_CHANNEL_SEL0_REG (DR_REG_PVT_BASE + 0x34)
+#define PVT_DBIAS_CHANNEL0_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL0_SEL_M  (PVT_DBIAS_CHANNEL0_SEL_V << PVT_DBIAS_CHANNEL0_SEL_S)
+#define PVT_DBIAS_CHANNEL0_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL0_SEL_S  25
+#define PVT_DBIAS_CHANNEL1_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL1_SEL_M  (PVT_DBIAS_CHANNEL1_SEL_V << PVT_DBIAS_CHANNEL1_SEL_S)
+#define PVT_DBIAS_CHANNEL1_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL1_SEL_S  18
+
+#define PVT_DBIAS_CHANNEL0_SEL_REG (DR_REG_PVT_BASE + 0x3c)
+#define PVT_DBIAS_CHANNEL0_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL0_CFG_M  (PVT_DBIAS_CHANNEL0_CFG_V << PVT_DBIAS_CHANNEL0_CFG_S)
+#define PVT_DBIAS_CHANNEL0_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL0_CFG_S  0
+
+#define PVT_DBIAS_CHANNEL1_SEL_REG (DR_REG_PVT_BASE + 0x40)
+#define PVT_DBIAS_CHANNEL1_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL1_CFG_M  (PVT_DBIAS_CHANNEL1_CFG_V << PVT_DBIAS_CHANNEL1_CFG_S)
+#define PVT_DBIAS_CHANNEL1_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL1_CFG_S  0
+
+#define PVT_DBIAS_CHANNEL2_SEL_REG (DR_REG_PVT_BASE + 0x44)
+#define PVT_DBIAS_CHANNEL2_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL2_CFG_M  (PVT_DBIAS_CHANNEL2_CFG_V << PVT_DBIAS_CHANNEL2_CFG_S)
+#define PVT_DBIAS_CHANNEL2_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL2_CFG_S  0
+
+#define PVT_DBIAS_CMD0_REG (DR_REG_PVT_BASE + 0x50)
+#define PVT_DBIAS_CMD0_PVT 0x7FF
+#define PVT_DBIAS_CMD0_PVT_S 0
+#define PVT_DBIAS_CMD0_OFFSET_FLAG 1
+#define PVT_DBIAS_CMD0_OFFSET_FLAG_S 16
+#define PVT_DBIAS_CMD0_OFFSET_VALUE 0x1F
+#define PVT_DBIAS_CMD0_OFFSET_VALUE_S 11
+
+#define PVT_DBIAS_CMD1_REG (DR_REG_PVT_BASE + 0x54)
+#define PVT_DBIAS_CMD1_PVT 0x7FF
+#define PVT_DBIAS_CMD1_PVT_S 0
+#define PVT_DBIAS_CMD1_OFFSET_FLAG 1
+#define PVT_DBIAS_CMD1_OFFSET_FLAG_S 16
+#define PVT_DBIAS_CMD1_OFFSET_VALUE 0x1F
+#define PVT_DBIAS_CMD1_OFFSET_VALUE_S 11
+
+#define PVT_DBIAS_CMD2_REG (DR_REG_PVT_BASE + 0x58)
+#define PVT_DBIAS_CMD2_PVT 0x7FF
+#define PVT_DBIAS_CMD2_PVT_S 0
+#define PVT_DBIAS_CMD2_OFFSET_FLAG 1
+#define PVT_DBIAS_CMD2_OFFSET_FLAG_S 16
+#define PVT_DBIAS_CMD2_OFFSET_VALUE 0x1F
+#define PVT_DBIAS_CMD2_OFFSET_VALUE_S 11
+
+#define PVT_DBIAS_TIMER_REG (DR_REG_PVT_BASE + 0x64)
+#define PVT_TIMER_EN    (BIT(31))
+#define PVT_TIMER_EN_M  (PVT_TIMER_EN_V << PVT_TIMER_EN_S)
+#define PVT_TIMER_EN_V  0x00000001U
+#define PVT_TIMER_EN_S  31
+#define PVT_TIMER_TARGET    0x0000FFFFU
+#define PVT_TIMER_TARGET_M  (PVT_TIMER_TARGET_V << PVT_TIMER_TARGET_S)
+#define PVT_TIMER_TARGET_V  0x0000FFFFU
+#define PVT_TIMER_TARGET_S  15
+
+#define PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x108)
+#define PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x10c)
+#define PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1c8)
+
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_S  0
+
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_M  (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_S  2
+
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_M  (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_S  2
+
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_M  (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_S  0

src/target/esp32p4/include/soc/reg_base.h

@@ -152,6 +152,7 @@
 #define DR_REG_LP_I2C_BASE            (DR_REG_LPPERIPH_BASE + 0x2000)
 #define DR_REG_LP_SPI_BASE            (DR_REG_LPPERIPH_BASE + 0x3000)
 #define DR_REG_I2C_ANA_MST_BASE       (DR_REG_LPPERIPH_BASE + 0x4000)
+#define DR_REG_LP_I2C_ANA_MST_BASE    DR_REG_I2C_ANA_MST_BASE
 #define DR_REG_LP_I2S_BASE            (DR_REG_LPPERIPH_BASE + 0x5000)
 #define DR_REG_LP_ADC_BASE            (DR_REG_LPPERIPH_BASE + 0x7000)
 #define DR_REG_LP_TOUCH_BASE          (DR_REG_LPPERIPH_BASE + 0x8000)

src/target/esp32p4/include/soc/regi2c_cpll.h

@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ *
+ * Register definitions for CPU_PLL (CPLL) on the internal regi2c bus.
+ * See ESP-IDF components/soc/esp32p4/include/soc/regi2c_cpll.h.
+ */
+
+#pragma once
+
+#define I2C_CPLL           0x67
+#define I2C_CPLL_HOSTID    0
+
+#define I2C_CPLL_OC_REF_DIV        2
+#define I2C_CPLL_OC_REF_DIV_MSB    3
+#define I2C_CPLL_OC_REF_DIV_LSB    0
+
+#define I2C_CPLL_OC_DCHGP        2
+#define I2C_CPLL_OC_DCHGP_MSB    6
+#define I2C_CPLL_OC_DCHGP_LSB    4
+
+#define I2C_CPLL_OC_ENB_FCAL        2
+#define I2C_CPLL_OC_ENB_FCAL_MSB    7
+#define I2C_CPLL_OC_ENB_FCAL_LSB    7
+
+#define I2C_CPLL_OC_DIV_7_0        3
+#define I2C_CPLL_OC_DIV_7_0_MSB    7
+#define I2C_CPLL_OC_DIV_7_0_LSB    0
+
+#define I2C_CPLL_OC_DCUR        6
+#define I2C_CPLL_OC_DCUR_MSB    2
+#define I2C_CPLL_OC_DCUR_LSB    0
+
+#define I2C_CPLL_OC_DHREF_SEL        6
+#define I2C_CPLL_OC_DHREF_SEL_MSB    5
+#define I2C_CPLL_OC_DHREF_SEL_LSB    4
+
+#define I2C_CPLL_OC_DLREF_SEL        6
+#define I2C_CPLL_OC_DLREF_SEL_MSB    7
+#define I2C_CPLL_OC_DLREF_SEL_LSB    6