WIP: feat(esp32p4): enable PVT auto-dbias and run CPU at CPLL/1 (IDFGH-18044) - #128
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WIP: feat(esp32p4): enable PVT auto-dbias and run CPU at CPLL/1 (IDFGH-18044)#128ginkgm wants to merge 3 commits into
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Port ESP-IDF PVT init/enable into the P4 stub clock path and raise CPU from CPLL/2 to CPLL/1 so voltage regulation matches the 400 MHz config.
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Add regi2c/CPLL register headers and configure CPLL at 400 MHz with CPU root divider /1, matching ESP-IDF rtc_clk_cpu_freq_to_cpll_mhz().
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Port ESP-IDF PVT init/enable into the P4 stub clock path and raise CPU from CPLL/2 to CPLL/1 so voltage regulation matches the 400 MHz config.
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