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This wiki describes the NetEmulation package developed in the Electronic Engineering Department at University College London. NetEmulation is a freely available simulation package for computer interconnect networks focusing on optical technologies. Unlike other network simulators, NetEmulation is written in SystemVerilog which, although slow for simulation, allows modules to be synthesised to obtain speed/area/power estimates for the control plane and also can form the basis of FPGA-based network demonstrators.

Please add to and improve the wiki as you work on your projects. Of course, text and diagrams which you add here can also be used for your reports which means you are not starting with a blank sheet of paper!

Requirements

NetEmulation is designed for use with Mentor Graphics Modelsim, although it could easily be adapted for other digital simulators. There is a free version of Modelsim available here, although for large simulations this will run slow.

Synthsis scripts (when included) are for Synopsys Design Compiler and Primetime.

Instructions

1. Download the code from here and extract into a new directory.

2. Move to the new directory and open modelsim (open a terminal and type modelsim & on UCL EE system)

3. Open the file config.sv. This contains the top level parameters for the network: number of ports, size of the payload, fifo depth etc. Comment the line `define VHDL if your network is in SystemVerilog. Uncomment it if your network is in VHDL. Make sure that `define SYNTHESIS is commented at this stage.

4. Open the net.do file. This is a modelsim simulation script. After the comment # Add network files here there is list of SystemVerilog files which define the simple optical network (they are all in the simple_optical directory). This defines which network will be used in the simulation.

5. In the modelsim transcript window, type do {net.do}. The simulation will start and display the test signals. The number of packets generated, received and the total latency for each port is displayed.

Publications

This code was used to obtain the results in the following papers. If you use the code for academic research, please cite them as appropriate:

(1)Shiyun Liu, Qixiang Cheng, Adrian Wonfor, Richard Penty, Ian White, Philip Watts, "A Low Latency Optical Top of Rack Switch for Data Centre Networks with Minimized Processor Energy Load ", Optical Fiber Communication Conference, San Francisco, California, March 2014.

(2)Van Laer, A; Watts, PM; (2012) Design of a speculative network adapter for shared memory communications in 45 nm CMOS. In: IEEE Optical Interconnects Conference 2012.

(3)Watts, PM; Moore, SW; Moore, AW; (2012) Energy Implications of Photonic Networks With Speculative Transmission. JOURNAL OF OPTICAL COMMUNICATIONS AND NETWORKING , Vol. 4 (6), pp 503 - 513.