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wiremod / wire Public

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Fork 346
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Issues 85
Pull requests 6
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Add Wire FPGA to main branch wire#3499

Merged

Anticept merged 238 commits intowiremod:masterwiremod/wire:masterfrom

llysdal:wire-fpgallysdal/wire:wire-fpgaCopy head branch name to clipboard

Feb 13, 2026

Conversation Commits238 (238)Checks Files changed

Merged

Add Wire FPGA to main branch wire#3499
Anticept merged 238 commits intowiremod:masterfrom
llysdal:wire-fpga

Commits

Commits on Feb 11, 2026

Added project files
llysdal
committed
Added input/outputs and connection drawing (nonfunctional so far)
llysdal
committed
Improved connection drawing
llysdal
committed
Flipped around connection structure, minor visual improvements
llysdal
committed
Added nodetypes, with new Input and Output gates
llysdal
committed
Made saving and loading functional
llysdal
committed
Fixed bug with tab closing
llysdal
committed
Fixed bugs related to saving
llysdal
committed
Added file naming and tab names
llysdal
committed
Made panel cover much nicer
llysdal
committed
Added uploading FPGA data to FPGA chip
llysdal
committed
Added node compiling
llysdal
committed
Compiler finds IO now, and chip updates its IO
llysdal
committed
Refactored mock-gates into real gate component
llysdal
committed
Added basic FPGA functionality
llysdal
committed
Added todo.txt
llysdal
committed
Moved compilation to serverside
llysdal
committed
Improved FPGA entity running
llysdal
committed
Added ability to create and remove gates (still in development)
llysdal
committed
Fixed net bug where indexes were ignored
llysdal
committed
Fixed execution bug regarding outputs
llysdal
committed
Added type colors
llysdal
committed
Added type checking to editor
llysdal
committed
Fixed visual bugs and improved colors
llysdal
committed
Added all input and output gates
llysdal
committed
Multiple outputs can now be drawn
llysdal
committed
Multiple outputs are now evaluated
llysdal
committed
Improved execution massively, inputs now get default values, execution order is monitored
llysdal
committed
Fixed error in last execution upgrade
llysdal
committed
Update todo.txt
llysdal
committed
Updated vector io gate names
llysdal
committed
Added execution benchmarking
llysdal
committed
Timed gates now work, and execution interval is adjustable
llysdal
committed
Added a way to change execution interval in the editor
llysdal
committed
Added input output labels in node editor
llysdal
committed
Improved execution
llysdal
committed
Fixed node editor related bugs
llysdal
committed
Made node grabbing a lot nicer
llysdal
committed
Inputs and outputs can now be named in the editor
llysdal
committed
Added normal constants, and made them work during execution
llysdal
committed
Added all constant values
llysdal
committed
Added infinite recursion protection
llysdal
committed
Update todo.txt
llysdal
committed
Attempted to implement "last" gate. all code commented out for future use
llysdal
committed
Made error messages better
llysdal
committed
Fixed client overlay
llysdal
committed
Added before-compilation validation on serverside
llysdal
committed
Fixed infinite loop detection
llysdal
committed
Added cpu time limits
llysdal
committed
Improved editor node creation a bit
llysdal
committed
Update nodeeditor.lua
llysdal
committed
Made error handling better
llysdal
committed
Revised input output name delegation
llysdal
committed
Added help text for when there is no nodes
llysdal
committed
Improved top bar color a bit
llysdal
committed
Update nodeeditor.lua
llysdal
committed
Update todo.txt
llysdal
committed
Apply force gates now work
llysdal
committed
Resetting now removes errors
llysdal
committed
Added support for compact gates
llysdal
committed
Chip clears errors on uploads now
llysdal
committed
Updated todo
llysdal
committed
Added support for duplicating
llysdal
committed
Fixed bug introduced by last commit
llysdal
committed
Improved tickrate detection
llysdal
committed
Use tickrate for lower limit on execution interval
llysdal
committed
Made spike quota optional
llysdal
committed
Updated todo and removed print
llysdal
committed
Added node selection, and selection moving and deleting
llysdal
committed
Update todo.txt
llysdal
committed
Added copying and pasting
llysdal
committed
Added upload limit
llysdal
committed
Added cool new toolgun screen
llysdal
committed
Improved error messages
llysdal
committed
Added functionality to tool screen
llysdal
committed
Made small text correction
llysdal
committed
Added first step to have looping
llysdal
committed
Update todo.txt
llysdal
committed
Fixed bug related to re-uploading chips
llysdal
committed
Update todo.txt
llysdal
committed
Removed vector2 and vector4 io gates
llysdal
committed
Renamed vector io gates
llysdal
committed
Renamed vector constant gate
llysdal
committed
Added in missing execution last gates
llysdal
committed
Update addon.json
llysdal
committed
Fixed saving bug
llysdal
committed
Updated the limit and added some permission work
llysdal
committed
Fixed bug where clients wouldn't create fpgachip dir
llysdal
committed
Various tweaks
llysdal
committed
Removed error message on no code specified
llysdal
committed
Added downloading
llysdal
committed
Fixed derma changing up order of execution interval and chip name
llysdal
committed
Update todo.txt
llysdal
committed
Fixed bug related to downloading empty chips
llysdal
committed
Made error detection on open better, and made shutdow hook work
llysdal
committed
Fixed frame being created on first tab
llysdal
committed
Update todo.txt
llysdal
committed
Made copying copy from center
llysdal
committed
Fixed bugs related to releasing mouse outside window
llysdal
committed
"Banned" string to memory and string from memory
llysdal
committed
Renamed highspeed-input to wirelink-input
llysdal
committed
Updated todo.txt
llysdal
committed
Fixed node pasting bug (non sequential)
llysdal
committed
Better default model
llysdal
committed
Made zoom better
llysdal
committed
Added logo
llysdal
committed
Fixed for gmad
llysdal
committed
Removed unnecessary tool_loader
llysdal
committed
QoL tweaks (_helloworld_, default to 0.1 execution interval, check if node connecting to itself)
llysdal
committed
Fixed whitelist issue
llysdal
committed
Updated logo
llysdal
committed
Update logo
llysdal
committed
Fixed horrible bug that limited executions to 50 cycles
llysdal
committed
Fixed bug where you couldn't create new file via filebrowser
llysdal
committed
Added colored connections
llysdal
committed
Changed edit behaviour to be more userfriendly
llysdal
committed
Added new cpu gates, with some initial conversion gates
llysdal
committed
Massively improved performance monitoring
llysdal
committed
Updated old logo
llysdal
committed
Update todo.txt
llysdal
committed
Update todo.txt
llysdal
committed
Fixed significant bug where you couldn't create/remove nodes after editing text
llysdal
committed
Update todo.txt
llysdal
committed
Removed unnecessary "output" lambda from io gates
llysdal
committed
Fixed wiring bug with entities
llysdal
committed
Added constant "self" and "owner" gates
llysdal
committed
Added new execution delta gate along with tickrate constant gate
llysdal
committed
Implemented postexecution hook, and created "previous" gates
llysdal
committed
"Previous" gates can now trigger an execution at next tick
llysdal
committed
Added ExecuteOn system
llysdal
committed
Added node colors
llysdal
committed
Added new FPGA Helper
llysdal
committed
Updated node colors to be a bit more subtle
llysdal
committed
Update help.lua
llysdal
committed
Update todo.txt
llysdal
committed
Fixed bug related to clients not getting help.lua
llysdal
committed
Fixed stupid bug with execute on trigger
llysdal
committed
Fixed last and previous gate behaviour (postcycle and postexecution)
llysdal
committed
Added new timed last execution gates, and improved Help section
llysdal
committed
Made timebench average over a longer period of time - more resistant to spikes
llysdal
committed
Added logic gates
llysdal
committed
Fixed lua syntax
llysdal
committed
Added half/full adders and subtractors
llysdal
committed
Reworked gate explorer to be able to handle preset order
llysdal
committed
Added "wide" logic gates
llysdal
committed
Added 4/8/16 bit adders
llysdal
committed
Added bit_operations gates
llysdal
committed
Temporary fix for unfocus bug
llysdal
committed
Fixed bug where FPGA would cause crash
llysdal
committed
Added global copy / paste buffer
llysdal
committed
Fixed bug with extra data not getting copied with nodes
llysdal
committed
Added "type annotations" to arithmetic gates
llysdal
committed
Changed output names of bit operation and logic gates
llysdal
committed
Added new text features for editor
llysdal
committed
Implemented multi connection drawing
llysdal
committed
Added memory gates (register and program counter)
llysdal
committed
Clarified that the program counter is edge triggered
llysdal
committed
Fail without errors on missing gates
llysdal
committed
Preparation work to add labels and comments
llysdal
committed
Added new Editor nodes, in the form of a label and comment gate
llysdal
committed
Implemented serverside FPGA code that deals with "visual" nodes
llysdal
committed
Edited colors to be a bit nicer
llysdal
committed
Added help for new features
llysdal
committed
Fixed error in help text
llysdal
committed
Added overlay, which shows status and auxillary info
llysdal
committed
Added align to grid functionality
llysdal
committed
Restructued nodeeditor.lua and added sections
llysdal
committed
Minor bugfix
llysdal
committed
Edited helloworld a bit, and made fonts nicer in help
llysdal
committed
Fixed error with "new file" button in tool
llysdal
committed
Added gate searching
llysdal
committed
WIP FPGA inside view
llysdal
committed
Update README.md
llysdal
committed
Improved the inside view - nodes are now drawn correctly
llysdal
committed
Made node compilation use local variables.
llysdal
committed
Added more inside view features
llysdal
committed
Added time hashing, to only send inside view to clients once
llysdal
committed
Implemented options syncing, and created option "allow inside view
llysdal
committed
Removed debug print statement
llysdal
committed
Fixed options behaving bad with empty chips
llysdal
committed
Fixed issue relating to edges in inside view
llysdal
committed
Only draw inside view inside the box, scissor rect the rest
llysdal
committed
Massively decreased net message size for inside views
llysdal
committed
Improved runtime error message a bit, adding clarity
llysdal
committed
Minor design tweak for FPGA Options
llysdal
committed
Fixed issue where error wouldn't show in overlay
llysdal
committed
Update todo.txt
llysdal
committed
Fixed bug when uploading empty chip
llysdal
committed
Added new selection gates
llysdal
committed
Fixed obscure bug related to FPGA view updating
llysdal
committed
Fixed net code usage bug in inside view timer
llysdal
committed
Delete todo.txt
llysdal
committed
Create .gitignore

Anticept
authored and
llysdal
committed
Create SECURITY.md

Anticept
authored and
llysdal
committed
Create CONTRIBUTING.md

Anticept
authored and
llysdal
committed
Update addon.json

Anticept
authored and
llysdal
committed
Update addon.json

Anticept
authored and
llysdal
committed
Made node editor use local gate helpers instead of methods
llysdal
committed
Moved DefaultValueForType into global shared space
llysdal
committed
Made node editor conform to coding style
llysdal
committed
Refactored various parts of the node editor
llysdal
committed
Fixed a function call not working in nodeeditor
llysdal
committed
Fixed use of deprecated wirelib function
llysdal
committed
Fixed error when downloading from fpga
llysdal
committed
Overhauled upload/download routines to compress data and decompress data
llysdal
committed
Refactored clientside inside view net code
llysdal
committed
Utilize WireLib.ParseEscapes for string constants

Denneisk
authored and
llysdal
committed
Fix rebase
llysdal
committed

Commits on Feb 12, 2026

fixing whitespace
llysdal
committed
Removed unused variables and functions
llysdal
committed
Replace surface.ScreenWidth and ScreenHeight with SrcW and SrcH
llysdal
committed
Replaced deprecated functions with new ones
llysdal
committed
Fixed inconsistent use of ~!
llysdal
committed
Removed empty if statement
llysdal
committed
Replaced ' ' with " "
llysdal
committed
Removed unnecessary parentheses
llysdal
committed
Fixed spelling mistake in Scr
llysdal
committed
Removed usages of ~=
llysdal
committed
Removed unused variables
llysdal
committed
Fixed bug with visual nodes
llysdal
committed
Changed help HTML
llysdal
committed
Convert indentation to using tabs
llysdal
committed
Merged wire fpga autoload into wire load
llysdal
committed
Removed trailing whitespace
llysdal
committed
Removed personal contact and author for fpga
llysdal
committed
Fixed error regarding execution count sometimes not being set
llysdal
committed
Removed some unnecessary comments
llysdal
committed
Remove more unnecessary comments
llysdal
committed
Moved fpgachip default file to wire default data generator
llysdal
committed
Moved fpga help html
llysdal
committed
Moved fpga help html to data_static
llysdal
committed
Update data version
Astralcircle
committed
Merge branch 'wire-fpga' of https://github.com/llysdal/wire into wire-fpga
Astralcircle
committed
Revert my commit
Astralcircle
committed
Merge branch 'wire-fpga' of https://github.com/llysdal/wire into wire-fpga
Astralcircle
committed
Recreate the folder every time it is deleted (fix from e2 editor)
Astralcircle
committed
Add check if client didn't downloaded content for some reason
Astralcircle
committed
Don't need AddCSLuaFile on client
Astralcircle
committed

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