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SimX-SST Integration Changes (No Memory Integration) - #298

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tinebp merged 18 commits into
vortexgpgpu:masterfrom
Jagadheesvaran:no_mem_changes
Apr 21, 2026
Merged

tinebp merged 18 commits into
vortexgpgpu:masterfrom
Jagadheesvaran:no_mem_changes

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This is a sample pull request to see if the changes pass all the CI tests.

@Jagadheesvaran
Jagadheesvaran marked this pull request as ready for review November 12, 2025 21:35
@tinebp
tinebp merged commit 13662f1 into vortexgpgpu:master Apr 21, 2026
tinebp added a commit that referenced this pull request May 6, 2026
… v3 API

This is the small targeted patch the master-into-v3 rebase plan calls for:
v3 wins all conflicts, but master's add-only sections at non-conflicting
locations leak through and need cleanup against v3's decomposed API.

main.cpp / processor.{cpp,h_impl}: remove master's PR #298 (SST cycle())
and master's DTM debug-mode block. Both reference vortex::Emulator, which
v3 deleted in commit 2062c86 (simx v3 TLM alignment). Session work
re-introduces both features against v3's Core / Scheduler / Operands
boundary.

sim/simx/dtm/*: delete master's DTM stack outright. Same reason — it
calls emulator_->get_warp / dcache_read / dcache_write throughout.
Session patch 0045 re-adds the v3-adapted version as new-file-mode
hunks, so the slot has to be empty for it to apply.

mem.cpp::RAM::copy: master added it with the legacy 1-arg get(addr).
v3's RAM::get takes (addr, bool allocate). Use allocate=true on dest
(write target) and allocate=false on src (zero-page on hole is the
established convention elsewhere in this file).

local_mem.cpp: drop the line_bits_ assignment — v3's LocalMem::Impl
no longer carries that field.

ringqueue.h / smallfunc.h / simobject.h: __assert → __vortex_assert.
The macro is named __vortex_assert in util.h; calling __assert at template
expansion time hits a dependent-name lookup error. (This one is a v3
self-bug introduced by a26b9e2 "simobject update", not strictly a
master-merge issue, but the build cannot finish without it.)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
tinebp added a commit that referenced this pull request May 6, 2026
Append §10 (Outcomes) capturing what actually happened during
execution on 2026-05-03:
  - the 'keep ours unless theirs is a bug fix' rule and where it
    overrode the original §4 plan
  - per-PR disposition deltas (especially #298 not adopted, #320
    arith wire-up, #310 OpenCL copybuf gated, #327 already absorbed)
  - known issues (pocl copybuf crash, MPI gating, intentional SST
    absence)
  - outstanding deferred work (9b5e664, a537f2a)
tinebp added a commit that referenced this pull request May 6, 2026
Documents how upstream PR #298 (Jagadheesvaran's SST integration)
should be ported onto the v3 TLM model. PR #298 was deferred per
master_merge_v3_proposal.md §10.2 because its mem_backend abstraction
conflicted with v3 Phase 5's single-source-of-truth-for-memory-state
rule (§3.3 of simx_v3_proposal.md).

The proposal:
- Identifies the architectural mismatch (mem_backend_dram/sst is
  pre-Phase-5; v3 has data-carrying MemReq/MemRsp through Cache+Memory)
- Repositions the SST plug-in boundary at Memory (not at LSU/cache)
- Adds a MemorySST class as a v3-aligned drop-in for Memory under
  USE_SST=1, with an SST::Link forwarding MemReq -> SST event ->
  MemRsp once SST responds
- Reuses the cycle()/start_kmu()/any_running() primitives already
  added in Round 6 for the DTM tick loop
- Phases the work (cycle skeleton, SST wrapper, real link, CI, docs)
- Carries upstream credits (Jagadheesvaran T S) on the files that
  port cleanly; documents which files are re-implemented for v3

Estimated 15-28 hours of focused work across 5 phases.
tinebp added a commit that referenced this pull request May 6, 2026
PR #298's SST integration was written against the legacy Emulator-based
Processor (took an Arch arg, used VX_DCR_BASE_* DCRs). v3 deleted Arch
and switched to KMU-based dispatch via VX_DCR_KMU_*. This commit ports
the SST source to v3:

- sim/simx/{processor.h,processor_impl.h,processor.cpp}: add
  Processor::cycle() — single-cycle entry that reuses the start_kmu()
  and any_running() primitives already added in Round 6 for DTM.
  Lazy-initializes (SimPlatform::reset + this->reset + kmu_->start)
  on first call, then SimPlatform::tick() per call.

- sim/simx/sst/vortex_simulator.h: drop Arch member, drop arch.h
  include. Constructor signature unchanged from caller's view.

- sim/simx/sst/vortex_simulator.cpp: drop Arch construction, switch
  Processor() to no-arg form, replace VX_DCR_BASE_* DCR setup with the
  full VX_DCR_KMU_* sequence (matching what main.cpp does — KMU needs
  startup addr, grid/block dims, warp step set up before the first
  cycle so warps actually launch).

- sim/simx/Makefile: under USE_SST=1, add sst/* sources to SRCS and
  pull SST element CXXFLAGS/LDFLAGS via sst-config. Also retarget the
  default 'all' to libsimx.so (the SST element library) instead of
  the simx executable when USE_SST=1, since SST loads the .so.

End-to-end SST validation still requires installing SST 15.1 + OpenMPI
4.1.6 via ci/sst_install.sh — see docs/proposals/sst_simx_v3_proposal.md
for the full integration phases. This commit covers Phase 1 (cycle()
plumbing) and most of Phase 2 (Component wrapper port). MemorySST
(Phase 3) — the actual SST-routed memory link — remains future work.
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