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[NPU] add A5/ascend950 support for A2E and E2A ops - #324

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[NPU] add A5/ascend950 support for A2E and E2A ops#324
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Register ascend950, gate SetCommEngine as HcclAccelerator::AIV on the 950 host build, and use the A5 MTE window layout (1MB state region, 1KB per-rank step) while 910C stays on the existing remoteRes path.

PLEASE FILL IN THE PR DESCRIPTION AND MAKE SURE THE CHECKLIST ITEMS HAVE BEEN CONSIDERED.

Purpose

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  • Related issue(s): #
  • Closing keyword, only if fully resolved: Closes #

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  • Out of scope:

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Essential PR Checklist
  • Purpose is clear and linked to public context when possible.
  • Scope is bounded.
  • Compatibility with vLLM v0.26.0 is considered.
  • No changes are made to the vLLM source checkout.
  • Plugin-owned classes or explicit dotted class paths are preferred over monkey patches.
  • Any compat shim or monkey patch is isolated, idempotent, version-guarded, documented, and tested.
  • Imports remain CPU-safe; CUDA-heavy work is delayed or GPU-gated.
  • Validation evidence is included, including skipped GPU tests when applicable.
  • Documentation impact is stated.

Register ascend950, gate SetCommEngine as HcclAccelerator::AIV on the 950
host build, and use the A5 MTE window layout (1MB state region, 1KB
per-rank step) while 910C stays on the existing remoteRes path.

Signed-off-by: wangyibo1005 <2633333316@qq.com>
@jiangkuaixue123

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Does the existing A3 functionality still work correctly with these changes?

@wangyibo1005

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Does the existing A3 functionality still work correctly with these changes?

Operators build respectively by indicating different SOC_VERSION, this pull request never changes any code of A3

@hsliuustc0106 hsliuustc0106 added enhancement New feature or request Ascend Ascend NPU platform and related changes labels Sep 14, 2026
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