Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
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Updated
May 2, 2021 - SourcePawn
Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
An open-source Ternary Content Addressable Memory (TCAM) compiler.
Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis
[ECE NTUA] 🖥️ Microprocessor Systems - Exercise Sets & Solutions (2019-2020)
This repository contains all the lecture slides, homeworks, Mid Terms, and the final project of the Computing Systems Architectures course by Prof. Azeez Bhavnagarwala, in Fall 2025 at NYU.
MARCH MSS 2114 SRAM Tester
This is our hardware design from our BsC thesis, Design of a hardware system for evaluating power consumption of SRAM memories with ECC
📚 Access comprehensive materials for the NYU Computing Systems Architecture course, including lectures, assignments, and exams from Fall 2025.
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