axi-bus

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Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus

CPU , 5-stage pipelined , with cache(I/D), TLB, and AXI interface implemented in Verilog. 五级流水线 MIPS CPU，支持前递、异常中断、TLB、缓存和 AXI 总线接口

simulator cpu pipeline cache verilog tlb axi cpu-simulator axi-bus

Xilinx UltraScale+ based HyperBus controller for HyperRam memories

fpga memory xilinx axi-bus memory-controller hyperram hyperbus

Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.

vhdl performance-analysis axi-bus axi-stream axi4 latency-analysis

Example workflow project for VHDL development.

workflow vhdl tcl vivado axi axi-bus tcl-scripts cocotb cocotb-testing

This is a hardware project of an inline memory compressor that reduces the amount of memory used by embedded systems

arm fpga hardware vhdl tcl verilog compressor axi-bus zynq-7000

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