memHierarchy: preserve same-address request order under MSHR pressure - #2711
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jake-ke wants to merge 110 commits into
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memHierarchy: preserve same-address request order under MSHR pressure#2711jake-ke wants to merge 110 commits into
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Cache::clockTick scans the per-cycle event buffer front-to-back, retrying any event it cannot accept. When an MSHR-full (or otherwise resource-blocked) request to a line is rejected mid-scan and a response later in the same scan frees the resource, a subsequent same-address request can be accepted ahead of the earlier one -- inverting two same-address requests issued by a single source. For back-to-back writes to the same line this silently drops an update: the older request lands last and overwrites the newer one, corrupting memory with no error raised. Fix: track addresses whose request was rejected this cycle in rejectedAddrsThisCycle_ and hold every later same-address request for the rest of that cycle's scan. On the next cycle the event buffer's FIFO order lets the earlier request claim the freed resource first. Responses are exempt so MSHR-draining events (GetXResp, WriteResp, AckPut, NACK, ...) always flow and forward progress is preserved. Observed under coherence_protocol=none with finite MSHRs, but the reorder is protocol-independent. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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Status Flag 'Pre-Test Inspection' - - This Pull Request Requires Inspection... The code must be inspected by a member of the Team before Testing/Merging |
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Fixes #2710 .
Problem
Cache::clockTickscans the per-cycle event buffer front-to-back, retrying any event it cannot accept. When a request to a line is rejected mid-scan (e.g. MSHR full) and a response later in the same scan frees the resource, a later same-address request can be accepted ahead of the earlier one — inverting two same-address requests from a single source. For back-to-back writes this silently drops an update: the older request lands last and overwrites the newer one, corrupting memory with no error raised. Most easily hit undercoherence_protocol=nonewith a finite MSHR, but the reorder is protocol-independent.Fix
Track addresses whose request was rejected this cycle in
rejectedAddrsThisCycle_and hold every later same-address request for the rest of that cycle's scan. On the next cycle the event buffer's FIFO order lets the earlier request claim the freed resource first. Responses are exempt so MSHR-draining events (GetXResp,WriteResp,AckPut,NACK, …) always flow and forward progress is preserved. Changes are confined tocacheController.{cc,h}(+22/−0).Testing
Happy to add a directed regression test if a reviewer can suggest a traffic pattern that reliably hits the window.