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[#860] MH1903 SCPU Support + ST7735 SPI LCD Controller#181

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[#860] MH1903 SCPU Support + ST7735 SPI LCD Controller#181
racerxdl wants to merge 1 commit intorenode:masterfrom
racerxdl:MH1903

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@racerxdl
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I added some preliminary support for the SecurCore MH1903, which is a SC300 (Cortex M4F with some security features + MPU). This allows to run the bootrom from AIR105 and MH1903 ( I shared a few here https://github.com/racerxdl/megahunt-bootroms/tree/main/MH1903 ) and few code like the one I did in my article about running code in a PAX D177 machine.

Not sure if you accept PR for adding features and MCU's but this should implement the basic so people that uses AIR105 MCU can simulate their designs nicely.

I still plan to add more features as long as I understand how the CPU works.

Implement complete peripherals for the MH1903 SoC:

- QSPI: Quad SPI Flash controller with Renode SPI framework integration
- OTP: One-Time Programmable memory controller
  - 10 control registers (CFG, CS, PROT, ADDR, PDATA, RO, ROLEN, RSVD, TIM, TIM_EN)
  - 2048 x 32-bit OTP data area
  - Proper reset values per MH1903 datasheet

- GPIO: General Purpose I/O ports A-F
  - BSRR (Bit Set/Reset Register) implementation for atomic pin control
  - Full register definitions for ODR, IDR, PUPDR, etc.
  - Integration with Renode GPIO framework

- UART: Universal Asynchronous Receiver/Transmitter (0-3)
  - Complete UART0-3 implementations with FIFO support
  - TX/RX callbacks for character transmission
  - Programmable baud rate via divisor latch

- SYSCTRL: System Control peripheral
  - Clock gating control registers
  - Power management registers
  - System configuration registers

@CLAassistant
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CLAassistant commented Jan 19, 2026

CLA assistant check
All committers have signed the CLA.

@racerxdl racerxdl changed the title Mh1903 [#860] MH1903 SCPU Support + ST7735 SPI LCD Controller Jan 20, 2026
@racerxdl
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For renode/renode#860

@PiotrZierhoffer
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Hi @racerxdl

Thanks for the contribution. It is quite significant and it may take us a while to go through it.

It would be the best if you could submit a companion PR on the Renode level with a .repl file and some kind of software that we could put in the resc file (as you mentioned in the issue).

It would be the best if the software was built in CI, so that we can replicate it internally.
A small nit - we typically try to name methods and content of the Registers enum in a more readable way (e.g. Control rather than CTRL), and use the shortened names in either comments or the name parameter of specific fields.

@racerxdl
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Hi @PiotrZierhoffer

Sure, I will do and put an example that can be built and run using the CI.
Will also update the register names, I was just following what was on datasheets but it does make sense to have a more readable names.

@Gissio
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Gissio commented Jan 25, 2026

I noticed you based your ST7735 controller on my ST7789 controller. Great work!

But it would be nice if you gave credit to the original code.

It would be also nice if you kept the keyboard/knob controllers, so other people can use them (even though your project doesn't).

@racerxdl
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I noticed you based your ST7735 controller on my ST7789 controller. Great work!

But it would be nice if you gave credit to the original code.

It would be also nice if you kept the keyboard/knob controllers, so other people can use them (even though your project doesn't).

Hmm, which controller? I certainly didnt based on yours 🤔 - I used the Litex Framebuffer as a base and my golang LCD emulator which only implements the small subset for actually making the LCD work.

@Gissio
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Gissio commented Jan 26, 2026

Apologies, my bad!

Implement complete peripherals for the MH1903 SoC:

- QSPI: Quad SPI Flash controller with Renode SPI framework integration
- OTP: One-Time Programmable memory controller
  - 10 control registers (CFG, CS, PROT, ADDR, PDATA, RO, ROLEN, RSVD, TIM, TIM_EN)
  - 2048 x 32-bit OTP data area
  - Proper reset values per MH1903 datasheet

- GPIO: General Purpose I/O ports A-F
  - BSRR (Bit Set/Reset Register) implementation for atomic pin control
  - Full register definitions for ODR, IDR, PUPDR, etc.
  - Integration with Renode GPIO framework

- UART: Universal Asynchronous Receiver/Transmitter (0-3)
  - Complete UART0-3 implementations with FIFO support
  - TX/RX callbacks for character transmission
  - Programmable baud rate via divisor latch

- SYSCTRL: System Control peripheral
  - Clock gating control registers
  - Power management registers
  - System configuration registers
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4 participants