Research Assistant, System on Chip Lab · Electrical Engineering Student
I'm a digital hardware designer and research assistant at the System on Chip Lab, where my work centers on Design for Testability and RTL-to-GDSII flows. I spend most of my time building open-source EDA tools like structural testability analyzers, fault simulators, MBIST generators, and logic optimization utilities that address gaps in the open-source silicon ecosystem.
On the design side, I work with Verilog and SystemVerilog for RTL, use cocotb and Verilator for simulation and verification, and have hands-on experience with synthesis flows using Yosys and OpenRAM. I'm also currently working on an AI accelerator for Mamba (SSMs), with a broader interest in hardware architectures for ML workloads.
Beyond open-source work, I have contributed to several projects for different teams and companies — including a Cache Controller, an MMU for a Linux-capable core, and Linux boot bring-up on a custom core and CVA6. I have also led interns and guided teams on their final year projects, covering synthesis and physical design of an ASCON-based PQC core, a GAN-based hardware accelerator, and an in-memory accelerator for transformer inference.
I write regularly on Medium covering DFT, scan architectures, fault modeling, synthesis, and computer architecture which are aimed at making these topics more accessible to students and early-career engineers.