wbgenplus

A WishBone³ bus device generator for VHDL, written in Python. Automatically produces VHDL interfaces to WishBone buses, saving manual boilerplate coding time.

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🔧 Features

• Generates VHDL entity/architecture/package/stub files for custom WishBone³ bus peripherals.
• Also generates matching register layouts as C header files for firmware/software use
• Python-based—no manual VHDL template editing required
• interfaces are described as XML structures
• Ideal for FPGA/ASIC projects using WishBone interconnects

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🛠️ Requirements

• Python 3.7+
• No external dependencies (pure Python tool)

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🚀 Installation

Clone the repo:

git clone https://github.com/mkreider/wbgenplus.git
cd wbgenplus

Run wbgenplus on the included example XMLs to get started