A generated core carries one register file and therefore one configuration. Time-multiplexed systems want N: one core serving several streams round-robin, each frame processed under its own complete configuration — the way a single hardware pipeline serves multiple cameras in production silicon, because nobody pays for N instances when one has the throughput.
The capability is generic: Reg and control_wrap() gain context banks — N shadow copies of the full register set, host-writable at any time, swapped atomically at a frame boundary by a context select. Table-backed state (grids, LUTs) needs the same treatment: banked, or reloaded during blanking, stated per block. And the property that makes switching SAFE is provable here rather than asserted: a block whose NumPy model is stateless across frames must generate RTL that is too — context isolation verified by the same bit-exact discipline as everything else.
Done means: an example in the suite running one core over interleaved frames from two configurations, bit-exact against running the same NumPy model twice with the respective configurations — under randomised backpressure, with a mid-stream host write to the inactive bank landing exactly at the next boundary and never earlier. Frame-granular switching only; line-interleaved is explicitly out of scope.
What it unlocks downstream: multi-camera pipelines on single-pipeline silicon — automotive and surveillance's favourite trade — and, for any user, A/B-testing two tunings on alternating frames with hardware guarantees about when each applies.
This is a sponsorable capability target (see the README's funding section). Sponsored work lands in the open tree immediately, MIT like everything else — sponsorship buys ordering and named credit, not exclusivity. Scope by email: s.rabykin@gmail.com.
A generated core carries one register file and therefore one configuration. Time-multiplexed systems want N: one core serving several streams round-robin, each frame processed under its own complete configuration — the way a single hardware pipeline serves multiple cameras in production silicon, because nobody pays for N instances when one has the throughput.
The capability is generic:
Regandcontrol_wrap()gain context banks — N shadow copies of the full register set, host-writable at any time, swapped atomically at a frame boundary by a context select. Table-backed state (grids, LUTs) needs the same treatment: banked, or reloaded during blanking, stated per block. And the property that makes switching SAFE is provable here rather than asserted: a block whose NumPy model is stateless across frames must generate RTL that is too — context isolation verified by the same bit-exact discipline as everything else.Done means: an example in the suite running one core over interleaved frames from two configurations, bit-exact against running the same NumPy model twice with the respective configurations — under randomised backpressure, with a mid-stream host write to the inactive bank landing exactly at the next boundary and never earlier. Frame-granular switching only; line-interleaved is explicitly out of scope.
What it unlocks downstream: multi-camera pipelines on single-pipeline silicon — automotive and surveillance's favourite trade — and, for any user, A/B-testing two tunings on alternating frames with hardware guarantees about when each applies.
This is a sponsorable capability target (see the README's funding section). Sponsored work lands in the open tree immediately, MIT like everything else — sponsorship buys ordering and named credit, not exclusivity. Scope by email: s.rabykin@gmail.com.