A simple implementation of a weight stationary systolic array multiplier. My goal for this project is to be able to run a useful neural net on my chip(whatever useful might mean). Due to the limited amount of space that I have, I will need to break up large matrices into many smaller ones. This will make my chip very slow.
For now, I have paused my work on the overall design since I dont think I will have time to finish it. My focus now is on systolic_array module which I hope to extensively test on the FPGA and hopefully Tiny Tapeout later