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SoC simulation running assembly test using GPIO verible-linter #368: Commit 32e9230 pushed by jeras
45s master
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SoC simulation running assembly test using GPIO R5P RISCOF Verification #31: Commit 32e9230 pushed by jeras
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Gowin: using SSRAM for UART FIFO, but are not present in the report R5P RISCOF Verification #30: Commit 2291a5e pushed by jeras
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Gowin: using SSRAM for UART FIFO, but are not present in the report verible-linter #367: Commit 2291a5e pushed by jeras
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Gowin: added PSRAM references verible-linter #366: Commit 9e177c5 pushed by jeras
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Gowin: added PSRAM references R5P RISCOF Verification #29: Commit 9e177c5 pushed by jeras
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cosmetic R5P RISCOF Verification #28: Commit 0bc7144 pushed by jeras
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cosmetic verible-linter #365: Commit 0bc7144 pushed by jeras
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Gowin IDE project, unfinished verible-linter #364: Commit d90b88d pushed by jeras
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Gowin IDE project, unfinished R5P RISCOF Verification #27: Commit d90b88d pushed by jeras
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synthesized mouse SoC for Tang Nano 9k board using OSS CAD Suite verible-linter #363: Commit f9e1583 pushed by jeras
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synthesized mouse SoC for Tang Nano 9k board using OSS CAD Suite R5P RISCOF Verification #26: Commit f9e1583 pushed by jeras
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whitespace R5P RISCOF Verification #25: Commit ed98a4e pushed by jeras
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whitespace verible-linter #362: Commit ed98a4e pushed by jeras
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porting to TCB-Lite and updated indenttion R5P RISCOF Verification #24: Commit cab8d16 pushed by jeras
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porting to TCB-Lite and updated indenttion verible-linter #361: Commit cab8d16 pushed by jeras
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modified degu to use TCB-Lite verible-linter #360: Commit 48a5c2e pushed by jeras
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modified degu to use TCB-Lite R5P RISCOF Verification #23: Commit 48a5c2e pushed by jeras
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updated mouse RISCOF to TCB-Lite verible-linter #359: Commit b1607b2 pushed by jeras
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updated mouse RISCOF to TCB-Lite R5P RISCOF Verification #22: Commit b1607b2 pushed by jeras
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Questa: updated to QuestaSetup-25.3.1.100-linux.run verible-linter #358: Commit 89e7400 pushed by jeras
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Questa: updated to QuestaSetup-25.3.1.100-linux.run R5P RISCOF Verification #21: Commit 89e7400 pushed by jeras
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Gowin FPGA: added README R5P RISCOF Verification #20: Commit 4c14ced pushed by jeras
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Gowin FPGA: added README verible-linter #357: Commit 4c14ced pushed by jeras
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RISCOF: removing debug tests from GitHub workflow R5P RISCOF Verification #19: Commit 0e9da78 pushed by jeras
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