[waveasm] Add NonEmittingOp trait and InsertOp to WaveASM dialect#1209
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Hardcode84 wants to merge 1 commit intoiree-org:mainfrom
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[waveasm] Add NonEmittingOp trait and InsertOp to WaveASM dialect#1209Hardcode84 wants to merge 1 commit intoiree-org:mainfrom
Hardcode84 wants to merge 1 commit intoiree-org:mainfrom
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harsh-nod
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Mar 31, 2026
harsh-nod
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Mar 31, 2026
| auto sourceIt = info.ranges.find(source); | ||
| while (sourceIt == info.ranges.end()) { | ||
| auto defOp = source.getDefiningOp<InsertOp>(); | ||
| if (!defOp) |
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maybe throw a warning or assertion here
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No, this is expected behavior, chains are always end on non-insert ops (pack).
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no but if you dont find the defining op, then shouldnt you raise a warning or assert?
harsh-nod
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Mar 31, 2026
Add NonEmittingOp trait to replace the hardcoded op list in HazardMitigation, and add InsertOp as the dual of ExtractOp for in-place sub-register replacement in wide registers. NonEmittingOp trait is applied to PackOp, ExtractOp, InsertOp, PrecoloredSRegOp, PrecoloredVRegOp, ConstantOp, DCEProtectOp, and YieldOp. HazardMitigation now checks the trait instead of maintaining a manual isa<> list. InsertOp replaces a single element in a wide register without extracting all words and rebuilding via PackOp. Liveness and regalloc handle chained inserts and shared-value copies. Used in handleFatRawBufferCast suppress-swizzle path for PackOp-built SRDs. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com> Signed-off-by: Ivan Butygin <ivan.butygin@gmail.com>
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harsh-nod
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Apr 1, 2026
| << "inserted value register class must match source register class: " | ||
| "source " | ||
| << vectorType << ", value " << valueType; | ||
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This verify function accepts inserted values wider than 1 register word, but LinearScanPass emits s_mov/v_mov with hardcoded size 1. A multi-word insert would only move the first word. Maybe enforce valueSize == 1?
harsh-nod
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Apr 1, 2026
| // so new non-emitting ops are covered automatically. | ||
| bool isNonEmittingOp(Operation *op) { | ||
| return isa<ExtractOp, PackOp, PrecoloredSRegOp, PrecoloredVRegOp, ConstantOp, | ||
| DCEProtectOp, YieldOp>(op); |
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why is precoloredAreg op made non emitting when it was not in this list? or was that a bug?
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Add NonEmittingOp trait to replace the hardcoded op list in HazardMitigation, and add InsertOp as the dual of ExtractOp for in-place sub-register replacement in wide registers.
NonEmittingOp trait is applied to PackOp, ExtractOp, InsertOp, PrecoloredSRegOp, PrecoloredVRegOp, ConstantOp, DCEProtectOp, and YieldOp. HazardMitigation now checks the trait instead of maintaining a manual isa<> list.
InsertOp replaces a single element in a wide register without extracting all words and rebuilding via PackOp. Liveness and regalloc handle chained inserts and shared-value copies. Used in handleFatRawBufferCast suppress-swizzle path for PackOp-built SRDs.