F4.6: gestión de energía + causa de reset (fix bucle IWDG F769)#84
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…WDG en F769 - Nuevo módulo `reset` (HAL F4 y F7, gemelos): lee y limpia RCC_CSR para distinguir la causa del último reset (power-on, brownout, pin, software, IWDG, WWDG, low-power) y la publica como `&'static str`. - El kernel almacena la causa de reset (`set_reset_cause`/`reset_cause`) y la consola la muestra en el comando `faults`. Los ejemplos la leen al arrancar. - Fix del bucle de reset IWDG en F769: la init de modo windowed perdía silenciosamente los writes de PR/RLR (corría con defaults /4 + 0xFFF → ~1 s), reseteando antes del primer kick. Se aplica la secuencia canónica (RM0410/ RM0090): arrancar el IWDG primero (KEY_START enciende el LSI), luego habilitar escritura y programar PR/RLR/WINR esperando a que cada flag SR.PVU/RVU/WVU se limpie. Espera acotada para no colgar el arranque si el LSI fallara. Validado en F407 (estable en safe-mode) y F769 (ya no entra en bucle de reset: supervisor vivo a 1/2/3/4/5 s en safe-mode). CI host: 29 tests OK. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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Resumen
reset(HAL F4 y F7, gemelos) que lee/limpiaRCC_CSRy publica la causa del último reset (power-on, brownout, pin, software, IWDG, WWDG, low-power). El kernel la almacena y la consola la muestra enfaults./4+0xFFF→ timeout ~1 s) y reseteaba antes del primer kick (~1.5 s). Se aplica la secuencia canónica RM0410/RM0090: KEY_START primero (enciende LSI), luego habilitar escritura y programar PR/RLR/WINR esperando a que cada flagSR.PVU/RVU/WVUse limpie (espera acotada).Validación
Test plan
🤖 Generated with Claude Code