Assistant Engineer – RTL Design and Verification at ADN Semiconductors
Electrical & Electronic Engineering Graduate | CGPA 3.475 | AUST
Passionate about VLSI Design Verification and semiconductor technologies. Combining technical skills with hands-on project experience and proven leadership in professional communities. Dedicated to continuous learning and delivering value in semiconductor verification projects.
ADN Semiconductors | January 2026 - Present
ADN DigiNet Ltd | September 2025 - December 2025
- Learning VLSI Design Verification methodologies and semiconductor technologies
- Building expertise in SystemVerilog, UVM, RTL design verification, and Vivado
- Utilizing development tools: VS Code, Git, Makefiles for verification workflows
IEEE Young Professionals Bangladesh | May 2025 - Present
- Coordinate flagship initiatives: YPCon 2025, IEEE YP Talk Series, Region 10 YP UpSkill – Bangladesh 2025
- Collaborate with IEEE Student Branches nationwide for YP-focused programs and outreach
- Bridge academic learning with industry-ready skills through IEEE Bangladesh Section partnerships
Verification & VLSI: SystemVerilog · UVM · RTL · Vivado · Cadence Virtuoso · Quartus Prime
Programming: C++ · C · Python
Tools & Platforms: VS Code · Git · Makefiles · STM32 · Arduino
Design & Simulation: Proteus · PSPICE · AutoCAD · STM32 Cube IDE
Other: LaTeX · Adobe Creative Suite · MS Office
Undergraduate Thesis | 2022-2023
- Implemented BMS with SOC estimation, voltage protection, and thermal management using STM32
- Developed real-time monitoring system with voltage and temperature sensors
- Tech Stack: STM32, Embedded C, Sensor Integration
- Designed and compared 8T, 10T, and 14T Full Adder architectures in Cadence Virtuoso
- Analyzed performance metrics including power, delay, and area trade-offs
- Tech Stack: Cadence Virtuoso, VLSI Design
- Designed custom 8-bit Simple-As-Possible (SAP) computer architecture
- Implemented instruction set and control logic
- Tech Stack: Digital Design, Computer Architecture
- Planned and designed complete network structure with IP addressing and subnetting
- Optimized network topology for departmental requirements
- Tech Stack: Networking, IP Design, Subnet Planning
BSc in Electrical & Electronic Engineering | CGPA 3.475
Ahsanullah University of Science & Technology | 2019 - 2023
Relevant Coursework: VLSI Design & Fabrication · Computer Architecture · Communication Systems · Power Electronics · Control Systems
IEEE AUST Student Branch - Chairperson (2023-2024)
Led to highest event count and membership since 2004 | Managed 57 officers | Hosted 2 national competitions
IEEE PES AUST - Vice Chair (2022-2023)
High-Performance Chapter Award | IEEE PES DAY Ambassador
AUST Innovation & Design Club - Joint Secretary (2022-2023)
Operations Lead for Mindsparks'22 (1,200+ participants, 30+ institutions)
🏅 Best Volunteer Award - IEEE AUST Student Branch (2022)
📧 Email: farhanmuhibefty@gmail.com
📱 WhatsApp: +8801521-561607
💼 LinkedIn: linkedin.com/in/farhanmuhibefty
🌐 Portfolio: Visit My Portfolio
📍 Location: Dhaka, Bangladesh
"Pursuing excellence in semiconductor design verification, one testbench at a time."
Open to opportunities in VLSI Design Verification & Semiconductor Engineering