Add minitests for DSP verification

minitests/dsp-io-registers/Makefile

@@ -0,0 +1,44 @@
+# Makefile for DSP IO registers minitests
+
+# Define the top-level design file
+TOP = top.v
+
+# Define the build directory
+BUILD_DIR = build
+
+# Define the output bitstream file
+BITSTREAM = $(BUILD_DIR)/design.bit
+
+# Define the Vivado project name
+PROJECT = design
+
+# Define the part number
+PART = xc7a35tcsg324-1
+
+# Define the Xilinx Vivado toolchain path
+VIVADO = vivado
+
+# Define the synthesis and implementation scripts
+SYNTH_SCRIPT = synth.tcl
+IMPL_SCRIPT = impl.tcl
+
+# Define the default target
+all: $(BITSTREAM)
+
+# Create the build directory
+$(BUILD_DIR):
+	mkdir -p $(BUILD_DIR)
+
+# Synthesize the design
+$(BUILD_DIR)/$(PROJECT).dcp: $(TOP) | $(BUILD_DIR)
+	$(VIVADO) -mode batch -source $(SYNTH_SCRIPT) -tclargs $(TOP) $(BUILD_DIR) $(PROJECT) $(PART)
+
+# Implement the design
+$(BITSTREAM): $(BUILD_DIR)/$(PROJECT).dcp
+	$(VIVADO) -mode batch -source $(IMPL_SCRIPT) -tclargs $(BUILD_DIR) $(PROJECT)
+
+# Clean the build directory
+clean:
+	rm -rf $(BUILD_DIR)
+
+.PHONY: all clean

minitests/dsp-io-registers/top.v

@@ -0,0 +1,28 @@
+module top (
+    input wire clk,
+    input wire [17:0] a,
+    input wire [17:0] b,
+    output wire [35:0] p
+);
+
+    // Instantiate the DSP48E1 primitive with input/output internal registers
+    DSP48E1 #(
+        .A_INPUT("DIRECT"),
+        .B_INPUT("DIRECT"),
+        .USE_DPORT("FALSE"),
+        .USE_MULT("MULTIPLY"),
+        .USE_SIMD("ONE48"),
+        .AREG(1),
+        .BREG(1),
+        .CREG(1),
+        .DREG(1),
+        .MREG(1),
+        .PREG(1)
+    ) dsp48e1_inst (
+        .CLK(clk),
+        .A(a),
+        .B(b),
+        .P(p)
+    );
+
+endmodule

minitests/dsp-multiplier/Makefile

@@ -0,0 +1,44 @@
+# Makefile for DSP multiplier minitests
+
+# Define the top-level design file
+TOP = top.v
+
+# Define the build directory
+BUILD_DIR = build
+
+# Define the output bitstream file
+BITSTREAM = $(BUILD_DIR)/design.bit
+
+# Define the Vivado project name
+PROJECT = design
+
+# Define the part number
+PART = xc7a35tcsg324-1
+
+# Define the Xilinx Vivado toolchain path
+VIVADO = vivado
+
+# Define the synthesis and implementation scripts
+SYNTH_SCRIPT = synth.tcl
+IMPL_SCRIPT = impl.tcl
+
+# Define the default target
+all: $(BITSTREAM)
+
+# Create the build directory
+$(BUILD_DIR):
+	mkdir -p $(BUILD_DIR)
+
+# Synthesize the design
+$(BUILD_DIR)/$(PROJECT).dcp: $(TOP) | $(BUILD_DIR)
+	$(VIVADO) -mode batch -source $(SYNTH_SCRIPT) -tclargs $(TOP) $(BUILD_DIR) $(PROJECT) $(PART)
+
+# Implement the design
+$(BITSTREAM): $(BUILD_DIR)/$(PROJECT).dcp
+	$(VIVADO) -mode batch -source $(IMPL_SCRIPT) -tclargs $(BUILD_DIR) $(PROJECT)
+
+# Clean the build directory
+clean:
+	rm -rf $(BUILD_DIR)
+
+.PHONY: all clean

minitests/dsp-multiplier/top.v

@@ -0,0 +1,22 @@
+module top (
+    input wire clk,
+    input wire [17:0] a,
+    input wire [17:0] b,
+    output wire [35:0] p
+);
+
+    // Instantiate the DSP48E1 primitive
+    DSP48E1 #(
+        .A_INPUT("DIRECT"),
+        .B_INPUT("DIRECT"),
+        .USE_DPORT("FALSE"),
+        .USE_MULT("MULTIPLY"),
+        .USE_SIMD("ONE48")
+    ) dsp48e1_inst (
+        .CLK(clk),
+        .A(a),
+        .B(b),
+        .P(p)
+    );
+
+endmodule