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[spi] Document nRF52 hardware SPI#6810

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anunayk:spi-nrf52-docs
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[spi] Document nRF52 hardware SPI#6810
anunayk wants to merge 2 commits into
esphome:nextfrom
anunayk:spi-nrf52-docs

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@anunayk anunayk commented Jun 20, 2026

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Documents nRF52 SPI support added in esphome/esphome#17078 (clock source 32 MHz; single fixed spi2 bus).

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esphome Bot previously requested changes Jun 20, 2026

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As this is a feature matched with a PR in https://github.com/esphome/esphome, please target your PR to the next branch and rebase.

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Please take a look at the requested changes, and use the Ready for review button when you are done, thanks 👍

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@esphome esphome Bot marked this pull request as draft June 20, 2026 04:36
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Review Change Stack

No actionable comments were generated in the recent review. 🎉

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Reviewing files that changed from the base of the PR and between 56705eb and 295ee03.

📒 Files selected for processing (1)
  • src/content/docs/components/spi.mdx

Walkthrough

The SPI component documentation gains two nRF52-specific additions: a note in the "Interface selection" section clarifying that Zephyr exposes only spi2, that interface: does not apply, only one SPI bus may be configured, and that clock/MOSI/MISO pins can be any free GPIOs; and a new nRF52 row (32 MHz) in the "Data rates" clock source table.

Changes

nRF52 SPI documentation

Layer / File(s) Summary
nRF52 interface note and clock source entry
src/content/docs/components/spi.mdx
Adds a Zephyr/nRF52-specific clarification block under "Interface selection" and inserts an nRF52 row specifying 32 MHz into the data-rates clock source table.

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✅ Passed checks (5 passed)
Check name Status Explanation
Title check ✅ Passed The title directly and clearly describes the main change: documenting nRF52 hardware SPI support in the SPI documentation file.
Description check ✅ Passed The description is directly related to the changeset, explaining that it documents nRF52 SPI support previously added, with specific details about the 32 MHz clock and spi2 bus.
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Reviewed commit: 295ee03742

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Comment thread src/content/docs/components/spi.mdx Outdated
Comment on lines +112 to +113
On nRF52 (Zephyr), a single hardware SPI bus (`spi2`) is available; the `interface:` option does not apply and only one
`spi:` bus may be configured. Assign `clk_pin`/`mosi_pin`/`miso_pin` to any free GPIOs.

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P2 Badge Retarget unreleased nRF52 SPI docs

This PR is targeting current, but the parent ESPHome change it documents (esphome/esphome#17078) is still a draft against dev; publishing this on the released docs branch would tell current-release users that nRF52 SPI works even though that implementation is not shipped yet. The repo instructions/CONTRIBUTING say feature docs should target next, so please retarget this docs change or hold it until the feature is released.

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This PR already targets next (its base branch is next, not current), which is the correct branch for unreleased feature docs per CONTRIBUTING. No retarget needed.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@anunayk anunayk changed the base branch from current to next June 20, 2026 04:52
@esphome esphome Bot added the next label Jun 20, 2026
@esphome esphome Bot dismissed their stale review June 20, 2026 04:52

Base branch has been corrected - dismissing previous review.

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As this is a feature matched with a PR in https://github.com/esphome/esphome, please target your PR to the next branch and rebase.

@anunayk anunayk marked this pull request as ready for review June 20, 2026 04:54
@esphome esphome Bot dismissed their stale review June 20, 2026 04:54

Stale

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Reviewed commit: 0cc582895a

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Comment thread src/content/docs/components/spi.mdx Outdated
ESPHome binds the nRF52 SPI to Zephyr's spi2 node (DT_NODELABEL(spi2)),
which the nRF52840 devicetree caps at 8 MHz (spi3 is the 32 MHz
controller). Fix the data-rate table and interface note accordingly.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
anunayk added a commit to anunayk/esphome that referenced this pull request Jun 20, 2026
PLATFORM_SPI_CLOCKS[PLATFORM_NRF52] was 32 MHz, but ESPHome binds the
nRF52 SPI to Zephyr's spi2 node (DEVICE_DT_GET(DT_NODELABEL(spi2)) =
SPIM2), which nrf52840.dtsi caps at DT_FREQ_M(8) = 8 MHz. Only spi3
(SPIM3) supports 32 MHz.

The reference clock drives _frequency_validator(): the old value let the
validator accept 16/32 MHz rates that SPIM2 cannot deliver (the requested
rate flows straight into Zephyr's spi_config.frequency, which the nrfx
driver silently clamps), and it computed the "closest available" divisor
grid against the wrong clock. 8 MHz both gates correctly and yields the
divisor grid (8M/4M/2M/1M/500k/250k/125k) that matches SPIM2's natively
supported frequencies.

Matches the docs fix in esphome/esphome.io#6810:
esphome/esphome.io#6810 (comment)

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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