phy/agilex_rgmii.py: RGMI Phy for Altera Agilex3/5 devices#202
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Thanks @trabucayre, this looks good! |
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This PR has for goal to integrates RGMII PHY for Altera Agilex3/5 devices.
Unlike others family (ECP5/S7/...) the tx_clk can't be derived from the
rx_clkand needs to be feedeed by another clock source or by the main PLL. This signal is provided by theref_rx_clkconstructor's parameter.A
CSRStatusis also required otherwise the fitter fails becausetennm_ph2_ddio_in'sregouthiis unused in the gateware forrx_ctl.Tested with terasic atum A3 Nano