[Deepin-Kernel-SIG] [linux 6.6.y] [Upstream] i915 fixes backport from v6.7 by opsiff · Pull Request #2253 · deepin-community/kernel

opsiff · 2026-11-05T11:36:14Z

Summary by Sourcery

Backport upstream i915 display fixes to improve DSC/link bandwidth allocation, platform initialization, and newer hardware power and AUX handling.

New Features:

Add shared display link-bandwidth management with adaptive per-pipe bpp limits and FDI bandwidth fallback handling.
Add Xe2 LPD display power-well and AUX register support.

Bug Fixes:

Improve DisplayPort DSC and FEC capability handling and link configuration to support output formats, MST, eDP, and bigjoiner bandwidth constraints.
Correct display capability initialization, connector detection when display is disabled, and several platform-specific display workarounds.

Enhancements:

Refine display state verification to obtain atomic old and new states directly and improve hardware state validation.
Centralize DP DSC capability data in connectors and modernize bpp and link-limit calculations across DP and FDI outputs.

Chores:

Backport the upstream i915 display fixes and infrastructure changes for Linux 6.6.y.

sourcery-ai · 2026-11-05T11:36:20Z

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sourcery-ai · 2026-11-05T11:36:43Z

Reviewer's Guide

Backports a broad set of i915 display fixes from v6.7, centered on a new iterative shared-link bandwidth framework and substantially rewritten DP/eDP DSC/BPP handling, while also adding Xe2 LPD power/AUX support, restructuring display-device initialization, modernizing modeset verification, and correcting legacy display paths and platform workarounds.

Sequence diagram for iterative i915 link bandwidth validation

sequenceDiagram
    participant Atomic as intel_atomic_check
    participant Config as intel_atomic_check_config
    participant BW as intel_link_bw_atomic_check
    participant FDI as intel_fdi_atomic_check_link
    participant Reduce as intel_link_bw_reduce_bpp

    Atomic->>Config: intel_atomic_check_config(state, limits)
    Config->>Config: intel_modeset_pipe_config(state, crtc, limits)
    Config-->>Atomic: configuration result
    Atomic->>BW: intel_link_bw_atomic_check(state, limits)
    BW->>FDI: intel_fdi_atomic_check_link(state, limits)
    FDI->>Reduce: intel_link_bw_reduce_bpp(state, limits, pipe_mask, reason)
    Reduce-->>FDI: reduced max_bpp_x16
    FDI-->>BW: -EAGAIN
    BW-->>Atomic: retry with updated limits
    Atomic->>Config: intel_atomic_check_config(state, limits)
    Config-->>Atomic: valid configuration

Sequence diagram for DP DSC link configuration fallback

sequenceDiagram
    participant DP as intel_dp_compute_link_config
    participant Limits as intel_dp_compute_config_limits
    participant DSC as intel_dp_dsc_compute_config
    participant BPP as intel_dp_dsc_compute_pipe_bpp
    participant DscLink as dsc_compute_link_config

    DP->>Limits: intel_dp_compute_config_link_bpp_limits(intel_dp, crtc_state, false, limits)
    DP->>DP: intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, limits)
    alt uncompressed link does not fit
        DP->>Limits: intel_dp_compute_config_link_bpp_limits(intel_dp, crtc_state, true, limits)
        DP->>DSC: intel_dp_dsc_compute_config(intel_dp, pipe_config, conn_state, limits, 64, true)
        DSC->>BPP: intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, conn_state, limits, timeslots)
        BPP->>DscLink: dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, limits, pipe_bpp, timeslots)
        DscLink-->>BPP: valid compressed_bpp and link lanes
        BPP-->>DSC: pipe_bpp and compressed_bpp
        DSC-->>DP: DSC configuration
    end

File-Level Changes

Change	Details	Files
Rework DP/eDP DSC and link-bandwidth computation to use explicit pipe/link BPP limits, connector-owned sink capabilities, and iterative shared-link fallback.	Add a shared link-bandwidth limit model and atomic-check retry loop. Refactor DP, eDP, MST, DSC, FEC, YUV420, and bigjoiner calculations around fractional link BPP and compressed BPP. Move DSC/FEC DPCD caching and decompression AUX ownership from the DP encoder to each connector. Replace FDI’s local BPP retry with centralized link-bandwidth reduction and apply limits to legacy PCH encoders.	`drivers/gpu/drm/i915/display/intel_link_bw.c` `drivers/gpu/drm/i915/display/intel_link_bw.h` `drivers/gpu/drm/i915/display/intel_dp.c` `drivers/gpu/drm/i915/display/intel_dp.h` `drivers/gpu/drm/i915/display/intel_dp_mst.c` `drivers/gpu/drm/i915/display/intel_fdi.c` `drivers/gpu/drm/i915/display/intel_fdi.h` `drivers/gpu/drm/i915/display/intel_display.c` `drivers/gpu/drm/i915/display/intel_display_types.h` `drivers/gpu/drm/i915/display/intel_crtc.c` `drivers/gpu/drm/i915/display/g4x_hdmi.c` `drivers/gpu/drm/i915/display/intel_crt.c` `drivers/gpu/drm/i915/display/intel_lvds.c` `drivers/gpu/drm/i915/display/intel_sdvo.c`
Add Xe2 display support for AUX register addressing and PICA power management.	Select generation-specific AUX control/data registers and remap AUX channels for display version 20+. Define and implement the Xe2 LPD PICA power well with enable, disable, status, and timeout handling. Install the Xe2 power-well map for display version 20 and update callers to the new AUX register macros.	`drivers/gpu/drm/i915/display/intel_dp_aux_regs.h` `drivers/gpu/drm/i915/display/intel_dp_aux.c` `drivers/gpu/drm/i915/display/intel_display_power_map.c` `drivers/gpu/drm/i915/display/intel_display_power_well.c` `drivers/gpu/drm/i915/display/intel_display_power_well.h`
Restructure display-device probing and runtime initialization so display capabilities are initialized independently and display disablement is handled centrally.	Move display probing earlier during device creation and split GMDID probing from generic probing. Move display runtime quirks and no-display feature disabling into the display-device layer. Replace the legacy display-enabled macro with a validated helper across connector detection and hotplug paths. Relocate display capability logging to display-driver registration and derive HAS_4TILE from display generation/platform.	`drivers/gpu/drm/i915/display/intel_display_device.c` `drivers/gpu/drm/i915/display/intel_display_device.h` `drivers/gpu/drm/i915/display/intel_display_driver.c` `drivers/gpu/drm/i915/i915_driver.c` `drivers/gpu/drm/i915/i915_drv.h` `drivers/gpu/drm/i915/i915_pci.c` `drivers/gpu/drm/i915/intel_device_info.c` `drivers/gpu/drm/i915/intel_device_info.h` `drivers/gpu/drm/i915/display/intel_crt.c` `drivers/gpu/drm/i915/display/intel_dp.c` `drivers/gpu/drm/i915/display/intel_dp_mst.c` `drivers/gpu/drm/i915/display/intel_dvo.c` `drivers/gpu/drm/i915/display/intel_hdmi.c` `drivers/gpu/drm/i915/display/intel_hotplug.c` `drivers/gpu/drm/i915/display/intel_panel.c` `drivers/gpu/drm/i915/display/intel_sdvo.c` `drivers/gpu/drm/i915/display/intel_tv.c`
Modernize post-commit hardware verification to obtain old/new states from the atomic transaction and make verification state read-only where appropriate.	Change C10 PLL, MPLLB, shared DPLL, CRTC, connector, and encoder verification APIs to consume intel_atomic_state. Allocate a separate hardware CRTC state for readback instead of mutating the old atomic state. Update commit-tail call sites and const-correct verification helpers.	`drivers/gpu/drm/i915/display/intel_modeset_verify.c` `drivers/gpu/drm/i915/display/intel_modeset_verify.h` `drivers/gpu/drm/i915/display/intel_dpll_mgr.c` `drivers/gpu/drm/i915/display/intel_dpll_mgr.h` `drivers/gpu/drm/i915/display/intel_cx0_phy.c` `drivers/gpu/drm/i915/display/intel_cx0_phy.h` `drivers/gpu/drm/i915/display/intel_snps_phy.c` `drivers/gpu/drm/i915/display/intel_snps_phy.h` `drivers/gpu/drm/i915/display/intel_display.c`
Apply upstream display correctness fixes and cleanup across legacy output, initialization, stepping workarounds, and zero-initialization patterns.	Enforce FDI-derived BPP limits for HDMI, CRT, LVDS, and SDVO paths. Update DG2 chicken-bit and CCS behavior and correct display runtime port masks. Fix generation-aware AUX register usage and simplify zero-initialized declarations.	`drivers/gpu/drm/i915/display/skl_universal_plane.c` `drivers/gpu/drm/i915/display/intel_acpi.c` `drivers/gpu/drm/i915/display/intel_cdclk.c` `drivers/gpu/drm/i915/display/intel_display_debugfs.c` `drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c` `drivers/gpu/drm/i915/display/intel_gmbus.c` `drivers/gpu/drm/i915/display/intel_plane_initial.c` `drivers/gpu/drm/i915/display/intel_wm.c` `drivers/gpu/drm/i915/Makefile`

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deepin-ci-robot · 2026-11-05T11:36:51Z

[APPROVALNOTIFIER] This PR is NOT APPROVED

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Copilot

🟡 Changes recommended

Unresolved NULL-pointer dereferences can cause kernel crashes, while incorrect DSC selection can discard supported color depths or exceed sink limits.

4 open issues

What changed in this PR

Backports upstream i915 display fixes from Linux 6.7 to Deepin’s 6.6 kernel, covering link bandwidth, display compression, power management, and modeset validation.

Changes:

Introduces shared link-bandwidth limits and iterative per-pipe color-depth fallback.
Reworks DP/eDP DSC configuration and moves DSC/FEC capabilities to connectors.
Updates display initialization, platform power controls, AUX addressing, and atomic-state verification.

File	Description
`drivers/gpu/drm/i915/selftests/mock_gem_device.c`	Explicitly probes display information for mock devices.
`drivers/gpu/drm/i915/Makefile`	Builds the new link-bandwidth module.
`drivers/gpu/drm/i915/intel_device_info.h`	Removes the stored 4-tile capability flag.
`drivers/gpu/drm/i915/intel_device_info.c`	Separates display initialization from general device setup.
`drivers/gpu/drm/i915/i915_pci.c`	Removes the platform’s stored 4-tile flag.
`drivers/gpu/drm/i915/i915_drv.h`	Relocates display helpers and removes obsolete macros.
`drivers/gpu/drm/i915/i915_driver.c`	Calls the separated display initialization routines.
`drivers/gpu/drm/i915/display/skl_universal_plane.c`	Removes an early-DG2 compression restriction.
`drivers/gpu/drm/i915/display/intel_wm.c`	Normalizes zero initialization.
`drivers/gpu/drm/i915/display/intel_tv.c`	Uses the display-enabled helper during detection.
`drivers/gpu/drm/i915/display/intel_snps_phy.h`	Updates the PLL verification interface.
`drivers/gpu/drm/i915/display/intel_snps_phy.c`	Reads PLL verification state from the atomic transaction.
`drivers/gpu/drm/i915/display/intel_sdvo.c`	Applies FDI depth limits and updates detection.
`drivers/gpu/drm/i915/display/intel_plane_initial.c`	Normalizes framebuffer-command initialization.
`drivers/gpu/drm/i915/display/intel_panel.c`	Uses the display-enabled helper for panel detection.
`drivers/gpu/drm/i915/display/intel_modeset_verify.h`	Simplifies modeset verification interfaces.
`drivers/gpu/drm/i915/display/intel_modeset_verify.c`	Uses separate hardware readback state during verification.
`drivers/gpu/drm/i915/display/intel_lvds.c`	Applies FDI depth limits before LVDS configuration.
`drivers/gpu/drm/i915/display/intel_link_bw.h`	Declares shared bandwidth limits and fallback interfaces.
`drivers/gpu/drm/i915/display/intel_link_bw.c`	Implements per-pipe bandwidth reduction and validation.
`drivers/gpu/drm/i915/display/intel_hotplug.c`	Uses the display-enabled helper for polling.
`drivers/gpu/drm/i915/display/intel_hdmi.c`	Updates the display-enabled detection check.
`drivers/gpu/drm/i915/display/intel_gmbus.c`	Normalizes HDCP buffer initialization.
`drivers/gpu/drm/i915/display/intel_fdi.h`	Exposes FDI depth-limit and link-check helpers.
`drivers/gpu/drm/i915/display/intel_fdi.c`	Integrates FDI validation with shared bandwidth fallback.
`drivers/gpu/drm/i915/display/intel_dvo.c`	Updates the display-enabled detection check.
`drivers/gpu/drm/i915/display/intel_dpll_mgr.h`	Updates shared PLL verification interfaces.
`drivers/gpu/drm/i915/display/intel_dpll_mgr.c`	Obtains PLL verification states from atomic state.
`drivers/gpu/drm/i915/display/intel_dp.h`	Defines separate pipe/link limits and revised DSC interfaces.
`drivers/gpu/drm/i915/display/intel_dp.c`	Reworks DSC depth selection, link configuration, and capability probing.
`drivers/gpu/drm/i915/display/intel_dp_mst.c`	Adapts MST configuration to connector capabilities and link limits.
`drivers/gpu/drm/i915/display/intel_dp_aux.c`	Passes device context to AUX register helpers.
`drivers/gpu/drm/i915/display/intel_dp_aux_regs.h`	Adds generation-specific AUX mappings and PICA registers.
`drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c`	Normalizes backlight buffer initialization.
`drivers/gpu/drm/i915/display/intel_display.c`	Adds bandwidth retries and updates verification calls.
`drivers/gpu/drm/i915/display/intel_display_types.h`	Adds connector capabilities and fractional-bpp helpers.
`drivers/gpu/drm/i915/display/intel_display_power_well.h`	Declares PICA power-well operations.
`drivers/gpu/drm/i915/display/intel_display_power_well.c`	Implements PICA controls and updates AUX access.
`drivers/gpu/drm/i915/display/intel_display_power_map.c`	Adds Xe2LPD PICA power-domain mappings.
`drivers/gpu/drm/i915/display/intel_display_driver.c`	Moves display capability logging to registration.
`drivers/gpu/drm/i915/display/intel_display_device.h`	Centralizes display capability and enabled-state helpers.
`drivers/gpu/drm/i915/display/intel_display_device.c`	Refactors probing and display runtime initialization.
`drivers/gpu/drm/i915/display/intel_display_debugfs.c`	Reports connector-owned DSC/FEC capabilities.
`drivers/gpu/drm/i915/display/intel_cx0_phy.h`	Updates the C10 PLL verification interface.
`drivers/gpu/drm/i915/display/intel_cx0_phy.c`	Reads C10 PLL verification state from atomic state.
`drivers/gpu/drm/i915/display/intel_crtc.c`	Initializes the maximum link-bpp limit.
`drivers/gpu/drm/i915/display/intel_crt.c`	Applies FDI depth limits and updates CRT detection.
`drivers/gpu/drm/i915/display/intel_cdclk.c`	Adds DSC bigjoiner minimum-clock calculations.
`drivers/gpu/drm/i915/display/intel_acpi.c`	Normalizes ACPI buffer initialization.
`drivers/gpu/drm/i915/display/g4x_hdmi.c`	Applies FDI depth limits to PCH HDMI configuration.

_{Review effort: Balanced}

+	/* Compressed BPP should be less than the Input DSC bpp */
+	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+	pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);


+	 * first downstream MST branch, via intel_dp's (root port) AUX.
+	 */
+	intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
+	intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);


Copilot

🟡 Changes recommended

DSC bandwidth and capability-validation defects can admit unsupported streams, and an MST capability read before connector initialization can turn an AUX failure into a kernel crash.

6 open issues

2 resolved since last review

_{Review effort: Balanced}

mainline inclusion from mainline-v6.7-rc1 category: bugfix All production DG2 cards have display stepping C0 or later. We can drop Wa_14013215631 (only applies to pre-C0) and make Wa_14010547955 unconditional (applies to everything B0 and beyond). Also drop the now-unused IS_DG2_DISPLAY_STEP macro. Bspec: 44477 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230816214201.534095-9-matthew.d.roper@intel.com (cherry picked from commit e50086f) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix We don't really need a feature flag for has_4tile since there's a well-defined cutover point (DG2) at which all new platforms started using Tile4 as their Y-major tiling layout. The GT side of the code already handles Tile4 vs legacy TileY with checks on the IP version rather than looking at the feature flag, and we can simplify the display code similarly (which will also make it more self-contained for re-use in the Xe driver). Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230810234618.3738870-4-matthew.d.roper@intel.com (cherry picked from commit 4ebf43d) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Move gmdid selection one abstraction level higher. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230912120537.2158209-2-jani.nikula@intel.com (cherry picked from commit a2c5757) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Don't hide display probe in device info code. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230912120537.2158209-3-jani.nikula@intel.com (cherry picked from commit 93caca6) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Fix some whitespace issues for register definitions and keep the defines for DP_AUX_CH_CTL and DP_AUX_CH_DATA in the right place: together with the bit definition. While at it add a TODO entry that those defines shouldn't be using an implicit dev_priv. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-10-lucas.demarchi@intel.com (cherry picked from commit dff8690) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix XELPDP_DP_AUX_CH_CTL() and XELPDP_DP_AUX_CH_DATA() use 2 ranges. Prefer using _PICK_EVEN_2RANGES() over PICK(). Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-11-lucas.demarchi@intel.com (cherry picked from commit 858c197) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix The address of CTL and DATA registers for DP AUX were changed in Xe2_LPD: now they are all in a single range, with CH_A and CH_B coming right after the USBC instances. Like was done when moving registers to PICA, use a helper macro to remap the ch passed to an index that can be used to calculate the right offset. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-12-lucas.demarchi@intel.com (cherry picked from commit 449f87e) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Add Display Power Well for Xe2_LPD. It's mostly the same as Xe_LPD+, so reuse the code. PGPICA1 contains type-C capable port slices which requires the well to power powered up, so add new power well definition for it. The DC_OFF fake power well will be added in a follow up commit. v2: Do not rmw as bit 31 is the only R/W bit in the register (Matt Roper) BSpec: 68886 Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-20-lucas.demarchi@intel.com (cherry picked from commit c2d9d8e) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

…tion mainline inclusion from mainline-v6.7-rc1 category: bugfix Separate the printing of display version and feature flags from the main driver probe to inside the display initialization. This is in alignment with isolating the display code from the main driver and helps Xe driver to resuse it. v2: Replace drm_info_printer with drm_debug_printer (Jani) Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921105954.2002469-1-balasubramani.vivekanandan@intel.com (cherry picked from commit 6a18ae5) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix There's no need for this to be a macro. Add some documentation too. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/480b9b697b2ffa0c8677115bd443ba633801c6c1.1696336887.git.jani.nikula@intel.com (cherry picked from commit fe63ea7) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Anything looking at display (runtime) info should be under display. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/41b53870ffa7bd41ccc337616c756c69326f05cf.1696336887.git.jani.nikula@intel.com (cherry picked from commit 5e72e75) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Move display related functionality from intel_device_info_runtime_init() to intel_display_device_info_runtime_init() and call the latter from the top level. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a2226a47a4450e75d867c2ac48665b387af0e42d.1696336887.git.jani.nikula@intel.com (cherry picked from commit b8eed6a) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Adjusting ->port_mask does not belong in intel_device_info_subplatform_init(), but rather intel_display_device_info_runtime_init(). Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1035800e623e13d5e7baf1215b07e7cdad5eb764.1696336887.git.jani.nikula@intel.com (cherry picked from commit 079d0b0) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix The state checker overwrites the old crtc state with the current hardware state. While that does save a kmalloc() it seems rather dubious as there might still be something that we need in the old crtc state. Stop doing that and just allocate a temporary state for the state checker. Should the extra malloc during the commit phase turn out too annoying we could of course preallocate one for each crtc, but let's proceed with the straightforward approch for now. And while at it let's mark the new crtc state as const to make sure the state checker doesn't mess it up. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231004155607.7719-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit 2745bdd) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix The DPLL state checker should not be modifying the crtc states, so make the const. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231004155607.7719-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit cfc7109) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Make life simpler by just passing in the atomic state + crtc instead of plumbing in all kinds of crtc states. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231004155607.7719-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit 4d6e198) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Passing in the atomic state + crtc state is a bit weird. The latter can be just the crtc (which is the normal calling convention used in a lot of other places). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231004155607.7719-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit 335aa75) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix Mark the remaining crtc states used by the state checker as const. There is no reason to ever mutate them here. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231004155607.7719-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit a4e7112) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.7-rc1 category: bugfix We're passing in a totally random mismash of things into the state checker. Clean it up to pass in the minimum needed. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231004155607.7719-11-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit 4627bef) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.9-rc1 category: bugfix Factor out intel_dp_config_required_rate() used by a follow-up patch enabling the DP tunnel BW allocation mode. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240220211841.448846-7-imre.deak@intel.com (cherry picked from commit e35cce9) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.9-rc1 category: bugfix Add intel_dp_max_link_data_rate() to get the link BW vs. the sink DPRX BW used by a follow-up patch enabling the DP tunnel BW allocation mode. The link BW can be below the DPRX BW due to a BW limitation on a link shared by multiple sinks. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240220211841.448846-11-imre.deak@intel.com (cherry picked from commit a4ea61b) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix The DSC HW state of DP connectors is read out during driver loading and system resume in intel_modeset_update_connector_atomic_state(). This function is called for all connectors though and so the state of DSI connectors will also get updated incorrectly, triggering a WARN there wrt. the DSC decompression AUX device. Fix the above by moving the DSC state readout to a new DP connector specific sync_state() hook. This is anyway the logical place to update the connector object's state vs. the connector's atomic state. Fixes: b2608c6 ("drm/i915/dp_mst: Enable MST DSC decompression for all streams") Reported-and-tested-by: Drew Davenport <ddavenport@chromium.org> Closes: https://lore.kernel.org/all/Zb0q8IDVXS0HxJyj@chromium.org Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240205132631.1588577-1-imre.deak@intel.com (cherry picked from commit a62e145) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Commit a62e145 ("drm/i915/dp: Fix connector DSC HW state readout") moved the DSC HW state readout to a connector specific hook, however only added the hook for DP MST connectors, not for DP SST ones. Fix adding the hook for SST connectors as well. This fixes the following warn on platforms where BIOS enables DSC: [ 66.208601] i915 0000:00:02.0: drm_WARN_ON(!connector->dp.dsc_decompression_aux || !connector->dp.dsc_decompression_enabled) ... [ 66.209024] RIP: 0010:intel_dp_sink_disable_decompression+0x76/0x110 [i915] ... [ 66.209333] ? intel_dp_sink_disable_decompression+0x76/0x110 [i915] ... [ 66.210068] intel_disable_ddi+0x135/0x1d0 [i915] [ 66.210302] intel_encoders_disable+0x9b/0xc0 [i915] [ 66.210565] hsw_crtc_disable+0x153/0x170 [i915] [ 66.210823] intel_old_crtc_state_disables+0x52/0xb0 [i915] [ 66.211107] intel_atomic_commit_tail+0x5cf/0x1330 [i915] [ 66.211366] intel_atomic_commit+0x39d/0x3f0 [i915] [ 66.211612] ? intel_atomic_commit+0x39d/0x3f0 [i915] [ 66.211872] drm_atomic_commit+0x9d/0xd0 [drm] [ 66.211921] ? __pfx___drm_printfn_info+0x10/0x10 [drm] [ 66.211975] intel_initial_commit+0x1a8/0x260 [i915] [ 66.212234] intel_display_driver_probe+0x2a/0x80 [i915] [ 66.212479] i915_driver_probe+0x7c6/0xc60 [i915] [ 66.212664] ? drm_privacy_screen_get+0x168/0x190 [drm] [ 66.212711] i915_pci_probe+0xe2/0x1c0 [i915] Fixes: a62e145 ("drm/i915/dp: Fix connector DSC HW state readout") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10410 Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240311145626.2454923-1-imre.deak@intel.com (cherry picked from commit 7a51a2a) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Pull the "does joiner need DSC?" check into a helper. MST will want to use this too at some point. Tested-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-9-ville.syrjala@linux.intel.com (cherry picked from commit aa09940) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix intel_dp_mst_compute_config() is missing the "does the joiner need DSC?" check despite claiming to have a lot of other joiner/dsc stuff in there (albeit disabled). Replicate the logic from the SST side. TODO: refactor all this duplicated code! Tested-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-10-ville.syrjala@linux.intel.com (cherry picked from commit 5a1527e) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Add a workaround to fix BS (blank start) to BS jitter issues on MST links when FEC is enabled. Neither Bspec requires this nor Windows clears the WA when disabling the output - presumedly because CHICKEN_MISC_3 gets reset after disabling the pipe/transcoder - so follow suit. Bspec: 50050, 55424 Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-2-imre.deak@intel.com (cherry picked from commit 9655a9a) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Add a workaround to fix BS jitter issues on MST links if the HBLANK period is less than 1 MTP. The WA applies only to UHBR rates while on non-UHBR the specification requires disabling it explicitly - presumedly because the register's reset value has the WA enabled. Bspec: 50050, 55424 Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-3-imre.deak@intel.com (cherry picked from commit 1af52d0) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Add a workaround to fix BS-BS jitter issues on MST links, aligning DPT/DPTP MTPs. Bspec: 50050, 55424 Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-4-imre.deak@intel.com (cherry picked from commit d4e745b) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Add a workaround to fix BS (blank start) to BS jitter fixes on non-UHBR MST/FEC and UHBR links. Bspec doesn't provide an actual WA ID for this. Bspec: 65448, 50054 Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-7-imre.deak@intel.com (cherry picked from commit 8f6372a) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix The expected link symbol clock unit when calculating the DSC DPT bpp limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit based on the crtc clock. As opposed to this port_clock is used - which has a 10 kbits/sec unit - with the resulting symbol clock in 10 kSymbols/sec units (disregarding the rounding error for the 13.5Gbps rate). Fix the calculation using the expected 10x factor. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-3-imre.deak@intel.com (cherry picked from commit 854ff3d) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix The DSC DPT bpp limit check should only fail if the available DPT BW is less than the required BW, fix the check accordingly. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-4-imre.deak@intel.com (cherry picked from commit 1ff65bf) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

… bpp limit mainline inclusion from mainline-v6.10-rc1 category: bugfix The DSC DPT interface BW limit check should take into account the link clock's (aka DDI clock in bspec) channel coding efficiency overhead. Bspec suggests that the FEC overhead needs to be applied, however HW people claim this isn't the case, nor is any overhead applicable. However based on testing various 5k/6k modes both on the DELL U3224KBA monitor and the Unigraf UCD-500 CTS test device, both the channel coding efficiency (which includes the FEC overhead) and an additional 3% overhead must be accounted for to get these modes working. Bspec: 49259 v2: - Apply an additional 3% overhead, add a commit log and code comment about these overheads and the relation to the Bspec BW limit formula. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-5-imre.deak@intel.com (cherry picked from commit fd13841) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix The DPT/DSC bpp limit should be accounted for on MTL platforms as well, do so. Bspec: 49259 Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-6-imre.deak@intel.com (cherry picked from commit e54cc6d) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Instead of checking each compressed bpp value against the maximum DSC/DPT bpp, simplify things by calculating the maximum bpp upfront and limiting the range of bpps looped over using this maximum. While at it add a comment about the origin of the DSC/DPT bpp limit. Bspec: 49259, 68912 Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-7-imre.deak@intel.com (cherry picked from commit 0f1ceee) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Factor out a function to check for 128b/132b channel coding support used by a follow-up patch in the patchset. v2: s/drm_dp_uhbr_channel_coding_supported()/drm_dp128b132b_supported() (Jani) Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Manasi Navare <navaremanasi@chromium.org> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240417141936.457796-1-imre.deak@intel.com (cherry picked from commit 8976bf1) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Factor out a function to check if an MST port is logical, used by a follow-up i915 patch in the patchset. v2: Move drm_dp_mst_aux_for_parent() forward declaration to the next patch. (Ankit) Cc: Lyude Paul <lyude@redhat.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-9-imre.deak@intel.com (cherry picked from commit ca5d9d7) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Add a function to get the AUX device of the parent of an MST port, used by a follow-up i915 patch in the patchset. v2: Move drm_dp_mst_aux_for_parent() forward declaration to this patch (Ankit) Cc: Lyude Paul <lyude@redhat.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-10-imre.deak@intel.com (cherry picked from commit 93cb409) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix The DPCD OUI of the logical port on a Dell UHBR monitor - on which the AUX device is used to enable DSC - is all 0. To detect if the HBLANK expansion quirk is required for this monitor use the OUI of the port's parent instead. Since in the above case the DPCD of both the logical port and the parent port reports being a sink device (vs. branch device) type, read the proper sink/branch OUI based on the DPCD device type. This is required by a follow-up patch enabling the quirk for the above Dell monitor. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-11-imre.deak@intel.com (cherry picked from commit 427c703) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Enabling the 5k@60Hz uncompressed mode on the MediaTek/Dell U3224KBA monitor results in a blank screen, at least on MTL platforms on UHBR link rates with some (<30) uncompressed bpp values. Enabling compression fixes the problem, so do that for now. Windows enables DSC always if the sink supports it and forcing it to enable the mode without compression leads to the same problem above (which suggests a panel issue with uncompressed mode). The same 5k mode on non-UHBR link rates is not affected and lower resolution modes are not affected either. The problem is similar to the one fixed by the HBLANK expansion quirk on Synaptics hubs, with the difference that the problematic mode has a longer HBLANK duration. Also the monitor doesn't report supporting HBLANK expansion; either its internal MST hub does the expansion internally - similarly to the Synaptics hub - or the issue has another root cause, but still related to the mode's short HBLANK duration. Enable the quirk for the monitor adjusting the detection for the above differences. v2: Rebase on drm_dp_128132b_supported() change. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240417142217.457902-1-imre.deak@intel.com (cherry picked from commit e78b8e8) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.13-rc1 category: bugfix The MST branch device may not support the number of DSC slices a mode requires, handle the error in this case. Fixes: 4e0837a ("drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation") Cc: stable@vger.kernel.org # v6.8+ Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241009110135.1216498-1-imre.deak@intel.com (cherry picked from commit 802a69b) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

…ble mode mainline inclusion from mainline-v6.13-rc1 category: bugfix If an MST branch device doesn't support DSC for a given mode, but the MST link has enough BW for the mode, assume that the branch device does support the mode using an uncompressed stream. Fixes: 55eaef1 ("drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk") Cc: stable@vger.kernel.org # v6.8+ Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241009110135.1216498-2-imre.deak@intel.com (cherry picked from commit 4e75c3e) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.16-rc1 category: bugfix Some DSI panel vendors end up hardcoding PPS params because of which it does not listen to the params sent from the source. We use the default config tables for DSI panels when using DSC 1.1 rather than calculate our own rc parameters. --v2 -Use intel_crtc_has_type [Jani] --v4 -Use a function to check Mipi dsi dsc 1.1 condition [Ankit] -Add documentation for using this condition [Ankit] -Rebase --v5 -Pass only the crtc_state [Jani] -Fixup the comment [Jani] -Check for dsc major version [Jani] -Use co-developed-by tag [Jani] --v6 -Add more definition of the issue and solution in the comment [Ankit] Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13719 Co-developed-by: William Tseng <william.tseng@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228152531.403026-1-suraj.kandpal@intel.com (cherry picked from commit c63d00e) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.10-rc1 category: bugfix Add a workaround to fix timing issues on links with DSC enabled - presumedly related to the audio functionality. Bspec requires enabling this workaround if audio is enabled on ADLP, however Windows enables it whenever DSC is enabled ADLP onwards; follow Windows. Bspec: 50490, 55424 v2: Fix WA code comment formatting. (Ankit) Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-5-imre.deak@intel.com (cherry picked from commit 377cc98 https://anongit.freedesktop.org/git/drm-intel.git drm-intel-next) Signed-off-by: Charlton Lin <charlton.lin@intel.com> Conflicts: drivers/gpu/drm/i915/display/intel_display.c (use MTL_CHICKEN_TRANS/CHICKEN_TRANS rather than deprecated hsw function) Tested-by: Charlton Lin <charlton.lin@intel.com> Reviewed-by: Manasi Navare <navaremanasi@chromium.org> Signed-off-by: Rakshith M O <rakshith.m.o@intel.com> (cherry picked from commit 9e9b8a4d44e67ae02432006981206167b2f6f346) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

mainline inclusion from mainline-v6.12-rc2 category: bugfix Atm it's assumed that all Synaptics MST branch devices support DSC, which is not exposed via a DP-to-DP peer device, rather a control flag in the branch device's UFP DPCD applying to all the streams going through it. This isn't true for all adapters with this branch device though (for instance the Cakitte USBC->2xHDMI adapter reported in the Closes link below doesn't support DSC). Fix the above by advertising the DSC decompression support only if the capability flag for this in the UFP DPCD is actually set. Cc: Lyude Paul <lyude@redhat.com> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12047 Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240909144650.2931258-1-imre.deak@intel.com (cherry picked from commit 70a6587 https://anongit.freedesktop.org/git/drm-misc.git drm-misc-fixes) Signed-off-by: Ap, Kamal <kamal.ap@intel.corp-partner.google.com> Reviewed-by: Shyam Sundar Radjacoumar <ssradjacoumar@google.com> Reviewed-by: Sean Paul <sean@poorly.run> Reviewed-by: Drew Davenport <ddavenport@chromium.org> (cherry picked from commit 1b9ebf7a6d8daa6bbd30449a28cc60dd11d12d02) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

Copilot

🟡 Changes recommended

Unresolved critical defects in power sequencing, DSC/MST handling, and scanout capability checks can cause kernel NULL dereferences, blank or corrupted displays, and unsupported hardware configurations.

12 open issues

1 resolved since last review

Defer aggregate MST bandwidth rejection to shared-link retry

_{Review effort: Max}

-	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
-						     min_bpp, limits,
-						     conn_state, 2 * 3, true);
+	crtc_state->pipe_bpp = max_bpp;


-	if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
-		return false;
-
 	return plane_id < PLANE_SPRITE4;


opsiff requested a balanced review from Copilot November 5, 2026 11:36

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opsiff force-pushed the linux-6.6.y-2026-11-05-i915-2 branch from 49882d1 to e05b42a Compare November 5, 2026 12:13

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Comment thread drivers/gpu/drm/i915/display/intel_dp.c Resolved

Comment thread drivers/gpu/drm/i915/display/intel_dp_mst.c Resolved

Comment thread drivers/gpu/drm/i915/display/intel_dp.c Resolved

Comment thread drivers/gpu/drm/i915/display/intel_dp.c Resolved

mattrope and others added 19 commits November 6, 2026 12:19

ideak and others added 25 commits November 6, 2026 14:01

opsiff force-pushed the linux-6.6.y-2026-11-05-i915-2 branch from fac52b9 to 6ccfbb5 Compare November 6, 2026 06:14

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opsiff merged commit 6ccfbb5 into deepin-community:linux-6.6.y Nov 6, 2026
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[Deepin-Kernel-SIG] [linux 6.6.y] [Upstream] i915 fixes backport from v6.7 - #2253

[Deepin-Kernel-SIG] [linux 6.6.y] [Upstream] i915 fixes backport from v6.7#2253
opsiff merged 145 commits into
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opsiff:linux-6.6.y-2026-11-05-i915-2

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Sequence diagram for iterative i915 link bandwidth validation

Sequence diagram for DP DSC link configuration fallback

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