[luoshance]

Upstream: no

AMD Zen 1 and Hygon are both affected by FPDSS(Floating Point Divider State Sampling): allows an attacker to leak data via floating point division unit. The upstream fix e55d98e ("x86/CPU: Fix FPDSS on Zen1") fix FPDSS by enable msr 0xc0011028 bit 9, which also can fix FPDSS on Hygon CPU.

Hygon-SIG: commit none hygon x86: hygon: Fix FPDSS on Hygon

Summary by Sourcery

Bug Fixes:

• Enable the Hygon floating-point divider state sampling mitigation to prevent potential data leakage through the floating-point division unit.

[sourcery-ai]

Reviewer's guide (collapsed on small PRs)

Reviewer's Guide

The Hygon CPU initialization path now mitigates the floating-point divider state sampling vulnerability by setting the shared AMD FP configuration MSR bit used for the Zen 1 fix, with a one-time diagnostic notice.

Sequence diagram for Hygon FPDSS mitigation during CPU initialization

sequenceDiagram
    participant Kernel
    participant HygonCPU
    participant MSR
    Kernel->>HygonCPU: init_hygon(c)
    HygonCPU->>HygonCPU: pr_notice_once()
    HygonCPU->>MSR: msr_set_bit(MSR_AMD64_FP_CFG, MSR_AMD64_FP_CFG_ZEN1_DENORM_FIX_BIT)
    MSR-->>HygonCPU: FPDSS mitigation enabled

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File-Level Changes

Change	Details	Files
Enable the existing Zen 1 FPDSS mitigation for Hygon processors during CPU initialization.	Log a one-time notice when the Hygon FPDSS mitigation is applied. Set the AMD floating-point configuration MSR bit that enables the Zen 1 denormal fix.	arch/x86/kernel/cpu/hygon.c

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[deepin-ci-robot]

Hi @luoshance. Thanks for your PR. 😃

[deepin-ci-robot]

Hi @luoshance. Thanks for your PR.

I'm waiting for a deepin-community member to verify that this patch is reasonable to test. If it is, they should reply with /ok-to-test on its own line. Until that is done, I will not automatically test new commits in this PR, but the usual testing commands by org members will still work. Regular contributors should join the org to skip this step.

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[deepin-ci-robot]

[APPROVALNOTIFIER] This PR is NOT APPROVED

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[Copilot]

🟢 Approval recommended

No active review issues are reported for the change enabling FPDSS mitigation during Hygon CPU initialization.

No open issues 🎉

What changed in this PR

This PR enables the existing floating-point divider state sampling (FPDSS) mitigation during Hygon CPU initialization, extending protection already used for AMD Zen 1.

Changes:

• Set the mitigation bit in MSR_AMD64_FP_CFG for Hygon CPUs.
• Emit a one-time notice that the mitigation is being enabled.

File	Description
arch/​x86/​kernel/​cpu/​hygon.c	Enable the FPDSS mitigation and add a one-time notice in init_hygon().

_{Review effort: Balanced}