feat(mps): prompt embedding cache + VAE latent cache for Apple Silicon#1774
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feat(mps): prompt embedding cache + VAE latent cache for Apple Silicon#1774huangyebiaoke wants to merge 1 commit into
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Add two caching layers to accelerate repeated generations:
1. **Prompt Embedding Cache** (TextEncoderCache):
- Already existed in WanAny2V pipeline, now extended to:
- DTT2V (diffusion_forcing.py) — T5 text encoding reused across seeds
- OviFusionEngine (ovi_fusion_engine.py) — batched text encoding cached
2. **VAE Latent Cache** (VAELatentCache — new):
- LRU cache (500MB default, CPU-stored, unified-memory-friendly)
- Hashed by tensor content (first/last elements + shape + mean/std)
- Wrapped at 6 key encode sites in WanAny2V:
- get_vae_latents() — per-reference-image caching
- _build_mocha_latents() — mocha ref image encoding
- SVI-Pro reference image encoding (image_ref, img_end_frame)
- SCAIL reference image encoding
Impact: repeat generations with same prompt/images skip T5 re-encoding
and VAE re-encoding of reference/guide images. On M4 Max, saves ~2-8s
per seed depending on model size.
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Rebased onto latest main (includes the MPS→main merge) and changed target branch from MPS to main. Ready for review. @deepbeepmeep This adds prompt embedding cache + VAE latent cache to reduce repeat-generation latency on Apple Silicon. |
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Summary
Adds two caching layers to accelerate repeat generations on Apple Silicon Macs:
1. Prompt Embedding Cache (TextEncoderCache)
The existing
TextEncoderCache(LRU, 100MB CPU-internal) was only used inWanAny2V. This PR extends it to:diffusion_forcing.py) — T5 encoding of prompt and negative prompt now cached across seedsovi_fusion_engine.py) — batched T5 encoding cached2. VAE Latent Cache (VAELatentCache — new)
New
shared/utils/vae_latent_cache.py:WanAny2V:get_vae_latents()— per-reference-image_build_mocha_latents()— mocha ref imagesImpact
Repeat generations with same prompt/images skip T5 re-encoding and VAE re-encoding of reference/guide images. Estimated savings: 2–8 seconds per seed depending on model size.
Risk
Low — caching only, no model/data changes. Cache stores detached CPU tensors, evicted on overflow. First run identical to before.