Several minor updates

.github/workflows/creator.yml

@@ -110,7 +110,6 @@ jobs:
     name: Build CLI (${{ matrix.os }})
     runs-on: ubuntu-latest
     needs: build-cli-wasm
-    if: github.event_name != 'pull_request'
     strategy:
       matrix:
         include:
@@ -198,6 +197,7 @@ jobs:
     name: Publish nightly release
     runs-on: ubuntu-latest
     needs: [build-cli-binaries, package-architectures, test]
+    if: github.event_name != 'pull_request'
     concurrency:
       group: nightly-release
       cancel-in-progress: false
@@ -229,7 +229,7 @@ jobs:
     name: Publish latest tagged release
     runs-on: ubuntu-latest
     needs: [build-cli-binaries, package-architectures, test]
-    if: github.ref_type == 'tag'
+    if: github.ref_type == 'tag' && github.event_name != 'pull_request'
     concurrency:
       group: stable-release
       cancel-in-progress: false

README.md

@@ -116,6 +116,30 @@
   <h2 align="center">Publications</h2>
 </div>
 
+### 2026
+
+<details>
+<summary>:newspaper: CREATOR-Sail: A RISC-V web simulator based on Sail ISA specification</summary>
+
+  * Journal paper: Journal of Systems Architecture
+  * Authors: Juan Carlos Cano-Resa, Félix García-Carballeira, Diego Camarmas-Alonso, Alejandro Calderón-Mateos
+  * [:link: Open publication](https://doi.org/10.1016/j.sysarc.2026.103809)
+  ```bibtex
+  @article{CANORESA2026103809,
+    title    = {CREATOR-Sail: A RISC-V web simulator based on Sail ISA specification},
+    journal  = {Journal of Systems Architecture},
+    volume   = {176},
+    pages    = {103809},
+    year     = {2026},
+    issn     = {1383-7621},
+    doi      = {https://doi.org/10.1016/j.sysarc.2026.103809},
+    url      = {https://www.sciencedirect.com/science/article/pii/S138376212600127X},
+    author   = {Juan Carlos Cano-Resa and Felix Garcia-Carballeira and Diego Camarmas-Alonso and Alejandro Calderon-Mateos},
+    keywords = {RISC-V, Sail, Web simulator, Extensible simulator, Instruction set architecture},
+  }
+  ```
+</details>
+
 ### 2025
 
 <details>
@@ -232,6 +256,7 @@
   * [:link: Open publication](https://doi.org/10.5281/zenodo.8378899)
   ```bibtex
   @proceedings{diego_camarmas_alonso_2023_8378899,
+    author    = {Diego Camarmas-Alonso and Felix Garcia-Carballeira and Alejandro Calderon-Mateos and Elías Del-Pozo-Puñal},
     title     = {{Integración del simulador CREATOR con hardware RISC-V: caso de estudio con microcontrolador ESP32}},
     year      = 2023,
     publisher = {Zenodo},
@@ -280,6 +305,7 @@
   * [:link: Open publication](http://doi.org/10.5281/zenodo.5130302)
   ```bibtex
   @proceedings{diego_camarmas_alonso_2021_5130302,
+    author    = {Diego Camarmas-Alonso and Felix Garcia-Carballeira and Alejandro Calderon-Mateos and Elías Del-Pozo-Puñal},
     title     = {{CREATOR: Simulador didáctico y genérico para la programación en ensamblador}},
     year      = 2021,
     publisher = {Zenodo},

architecture/6502.yml

@@ -14,11 +14,11 @@ config:
   start_address: 0x0
   pc_offset: 0
 
-components:
+register_files:
   - name: Control registers
-    type: ctrl_registers
+    type: ctrl
     double_precision: false
-    elements:
+    registers:
       - name:
           - PC
         nbits: 8
@@ -30,9 +30,9 @@ components:
           - write
           - program_counter
   - name: Integer registers
-    type: int_registers
+    type: int
     double_precision: false
-    elements:
+    registers:
       - name:
           - A
         encoding: 0

architecture/MIPS32.yml

@@ -19,11 +19,11 @@ config:
     - name: CreatorAssembler
       description: "Default CREATOR assembler"
 
-components:
+register_files:
   - name: Control registers
-    type: ctrl_registers
+    type: ctrl
     double_precision: false
-    elements:
+    registers:
       - name:
           - PC
         nbits: 32
@@ -128,9 +128,9 @@ components:
           - read
           - write
   - name: Integer registers
-    type: int_registers
+    type: int
     double_precision: false
-    elements:
+    registers:
       - name:
           - "0"
           - zero
@@ -462,9 +462,9 @@ components:
           - read
           - write
   - name: 32-bit FP registers
-    type: fp_registers
+    type: float
     double_precision: false
-    elements:
+    registers:
       - name:
           - f0
           - FP0

architecture/RISCV/RV32IMFD.yml

@@ -49,11 +49,11 @@ extensions:
     description: "RV32/RV64 Privileged instructions"
     type: extension
 
-components:
+register_files:
   - name: Control registers
-    type: ctrl_registers
+    type: ctrl
     double_precision: false
-    elements:
+    registers:
       - name:
           - pc
         nbits: 32
@@ -149,9 +149,9 @@ components:
           - write
 
   - name: Integer registers
-    type: int_registers
+    type: int
     double_precision: false
-    elements:
+    registers:
       - name:
           - x0
           - zero
@@ -490,9 +490,9 @@ components:
           - write
 
   - name: Floating point registers
-    type: fp_registers
+    type: float
     double_precision: true
-    elements:
+    registers:
       - name:
           - f0
           - ft0
@@ -2075,25 +2075,6 @@ instructions:
         debugging environment. It generates a breakpoint exception and performs
         no other operation.
 
-    # TODO: delete this when devices exist
-    - name: print_int
-      type: Syscall
-      template: Custom
-      fields:
-        - field: opcode
-          value: "1110011"
-        - field: funct12
-          type: cop
-          startbit: 31
-          stopbit: 20
-          value: "000000000010"
-        - field: zeros
-          type: cop
-          startbit: 19
-          stopbit: 7
-          value: "0000000000000"
-      definition: "CAPI.SYSCALL.print(registers.a0, 'int32');"
-
   M:
     #   ____ __     __ _____ ____   __  __
     #  |  _ \\ \   / /|___ /|___ \ |  \/  |
@@ -2213,7 +2194,9 @@ instructions:
         - field: funct3
           value: "110"
       definition: |
-        registers[rd] = registers[rs1] % registers[rs2];
+        registers[rd] = CAPI.FP.int2uint(
+          CAPI.FP.uint2int(registers[rs1]) % CAPI.FP.uint2int(registers[rs2])
+        );
       help: Perform an XLEN-bit by XLEN-bit signed integer reminder of rs1 by
         rs2.
 

architecture/RISCV/RV64IMFD.yml

@@ -50,11 +50,11 @@ extensions:
     description: "RV32/RV64 Privileged instructions"
     type: extension
 
-components:
+register_files:
   - name: Control registers
-    type: ctrl_registers
+    type: ctrl
     double_precision: false
-    elements:
+    registers:
       - name:
           - pc
         nbits: 64
@@ -150,9 +150,9 @@ components:
           - write
 
   - name: Integer registers
-    type: int_registers
+    type: int
     double_precision: false
-    elements:
+    registers:
       - name:
           - x0
           - zero
@@ -491,9 +491,9 @@ components:
           - write
 
   - name: Floating point registers
-    type: fp_registers
+    type: float
     double_precision: true
-    elements:
+    registers:
       - name:
           - f0
           - ft0
@@ -2412,7 +2412,9 @@ instructions:
         - field: funct3
           value: "110"
       definition: |
-        registers[rd] = registers[rs1] % registers[rs2];
+        registers[rd] = CAPI.FP.int2uint(
+          CAPI.FP.uint2int(registers[rs1]) % CAPI.FP.uint2int(registers[rs2])
+        );
       help: Perform an XLEN-bit by XLEN-bit signed integer reminder of rs1 by
         rs2.
 
@@ -2447,7 +2449,7 @@ instructions:
         - field: funct3
           value: "010"
         - field: rd
-          type: SFP-Reg
+          type: DFP-Reg
       definition: |
         let addr = registers[rs1] + imm;
         if (CAPI.VALIDATION.isMisaligned(addr, 4))
@@ -3076,7 +3078,7 @@ instructions:
         - field: funct3
           value: "010"
         - field: rs2
-          type: SFP-Reg
+          type: DFP-Reg
       definition: |
         let value = registers[rs2] & 0xFFFFFFFFn;
         let addr = registers[rs1] + imm;
@@ -3107,7 +3109,7 @@ instructions:
         let addr = registers[rs1] + imm;
         if (CAPI.VALIDATION.isMisaligned(addr, 8))
             CAPI.VALIDATION.raise('The memory must be aligned');
-        registers[rd] = CAPI.MEM.read(8, 8, rd, false);
+        registers[rd] = CAPI.MEM.read(addr, 8, rd, false);
       help: Load a double-precision floating-point value from memory into floating-point register rd.
 
     - name: fadd.d
@@ -3182,7 +3184,7 @@ instructions:
         - field: rd
           type: DFP-Reg
         - field: rs1
-          type: SFP-Reg
+          type: DFP-Reg
         - field: funct7
           value: "0100001"
         - field: funct5
@@ -3280,7 +3282,7 @@ instructions:
           optional: true
           order: 3
         - field: rd
-          type: SFP-Reg
+          type: DFP-Reg
         - field: rs1
           type: DFP-Reg
       preoperation: |
@@ -4138,30 +4140,30 @@ pseudoinstructions:
     - name: fabs.s
       fields:
         - field: rs1
-          type: SFP-Reg
+          type: DFP-Reg
           suffix: ","
         - field: rs2
-          type: SFP-Reg
+          type: DFP-Reg
       definition: |
         fsgnjx.s rs1, rs2, rs2;
 
     - name: fmv.s
       fields:
         - field: rs1
-          type: SFP-Reg
+          type: DFP-Reg
           suffix: ","
         - field: rs2
-          type: SFP-Reg
+          type: DFP-Reg
       definition: |
         fsgnj.s rs1, rs2, rs2;
 
     - name: fneg.s
       fields:
         - field: rs1
-          type: SFP-Reg
+          type: DFP-Reg
           suffix: ","
         - field: rs2
-          type: SFP-Reg
+          type: DFP-Reg
       definition: |
         fsgnjn.s rs1, rs2, rs2;
   D: