FPGA-Labs

Solutions of the Intel Digital Logic FPGA Academy labs all written in VHDL and another extra labs on FPGA Timing and CDC

Our Board

Terasic DE0-CV

Documentation ✅ ❌

Labs	Status	Tested on board?
lab1	completed	✅
lab2	completed	✅
lab3	completed	✅
lab4	completed	✅
lab5	completed	✅
lab6	completed	✅
lab7	completed	✅
lab8	completed	✅
lab9	completed	✅
labA	completed	✅
labB
labC
labD
EXTRAS	---------	----------------
Timing Lab	completed	✅
nois_processor	completed	❌

Authors

• @Rufaida-Kassem
• @Muhamed-Sayed
• @Ahmed-ata112