The production board schematic description on sht. 1 says "X4 PCIE TIME CARD", and four lanes are routed between the edge connector and FPGA (schematic and board). However, the production FPGA only uses a single lane. This lane is correctly attached to the TX0 and RX0 pairs in the board design.
It works, no doubt, but there may be missed expectations for new users.
If going to an x4 channel, during FPGA synthesis are the additional pairs guaranteed to go to the pins already connected on the board?
[ from Vivado block diagram ]
The production board schematic description on sht. 1 says "X4 PCIE TIME CARD", and four lanes are routed between the edge connector and FPGA (schematic and board). However, the production FPGA only uses a single lane. This lane is correctly attached to the TX0 and RX0 pairs in the board design.
It works, no doubt, but there may be missed expectations for new users.
If going to an x4 channel, during FPGA synthesis are the additional pairs guaranteed to go to the pins already connected on the board?
[ from Vivado block diagram ]
