[ENG-2097] Small fix for annotate_ff_width

[stanminlee]

FF width pass will count the number of regs to get the proper width

[linear-code]

ENG-2097

[greptile-apps]

Greptile Summary

This PR replaces the annotate_ff_width pass's width measurement (reading WIDTH param or Q-port size) with a counting strategy: cells are grouped by their "base name" (stripping a trailing numeric index like [3]), and each cell is annotated with the group count.

• New ff_base_name helper strips a trailing [N] numeric suffix so that split cells such as reg[0]…reg[7] map to the shared base reg and are counted together.
• Counting replaces per-cell width measurement: ff_width is now set to the number of FF cells sharing the same base name rather than the cell's actual WIDTH parameter or Q-port bit-width.
• The approach is semantically correct only when invoked after splitcells has already produced the [N]-indexed cells; however, the current call site in synthesis.py invokes the pass before splitcells, so normal multi-bit FFs receive ff_width=1 and the cg_min_ff_size threshold in clockgate is effectively disabled.

Confidence Score: 3/5

The new counting logic requires the pass to run after register splitting, but the existing synthesis pipeline calls it before; all multi-bit FFs would receive an incorrect width of 1, silently disabling clock-gating.

The central change inverts the call-order assumption: counting [N]-indexed cells only produces the right answer when they already exist in the design, yet synthesis.py still places this pass before splitcells. Every regular multi-bit FF ends up with ff_width=1, making cg_min_ff_size a no-op and suppressing the clock-gating optimization that depends on it.

passes/silimate/annotate_ff_width.cc — verify the intended call-order relative to splitcells, and confirm synthesis.py is updated accordingly.

Important Files Changed

Filename	Overview
passes/silimate/annotate_ff_width.cc	Replaces WIDTH-param/Q-port width measurement with a base-name counting approach; correct only when called after splitcells, but the current synthesis.py call site is before splitcells, causing ff_width=1 for all non-array FFs and silently disabling cg_min_ff_size gating.

Sequence Diagram

sequenceDiagram
    participant S as synthesis.py
    participant AFF as annotate_ff_width
    participant SC as splitcells
    participant CG as clockgate

    S->>AFF: run (before split)
    Note over AFF: OLD: reads WIDTH param / Q-port size → correct width (e.g. 8)
    Note over AFF: NEW: counts cells by base name → always 1 (no [N] suffix yet)
    AFF-->>S: ff_width attr set on each cell

    S->>SC: splitcells -format [N]
    Note over SC: reg (WIDTH=8) → reg[0]…reg[7], each WIDTH=1

    S->>CG: clockgate -min_ff_size N
    CG->>CG: read ff_width attr
    Note over CG: OLD ff_width=8 → orig_w ≥ threshold → gate applied
    Note over CG: NEW ff_width=1 → orig_w < threshold → all FFs skipped

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