Refactor packet_handler RTL for synthesis quality and handshake correctness

[kiro-agent]

This pull request was created by @kiro-agent on behalf of @RafailDD 👻

Comment with /kiro fix to address specific feedback or /kiro all to address everything.
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Summary

Refactor packet_handler.v for synthesis quality and handshake correctness, based on the jules-experimenting branch tip.

Synthesizability improvements

Change	Why it matters
Move fifo_mem and packetTracker writes into their own reset-free always blocks	Standard RAM-inference template — lets synthesis map both memories to distributed/block RAM instead of resettable flip-flops.
Replace the for (i=0; i<32; i=i+1) packetTracker[i] <= 0; reset loop with a 32-bit tracker_valid register	Saves ~1024 reset-bearing flip-flops; only 32 FFs (tracker_valid) are reset; the data array is RAM-inference friendly.
Bound the packetTracker index to 5 bits (in_streamId[4:0] - 1)	Previously a 16-bit subtraction indexed a 32-deep array — out-of-range behaviour was undefined.
fifo_full = fifo_count[FIFO_AW] instead of fifo_count == 9'd256	One bit lookup vs. 9-bit compare.
(* fsm_encoding = "one_hot" *) attribute on state	Preserves the intended one-hot encoding through Vivado/Synplify; other tools ignore unknown attributes.
next_state = state; default at top of comb block	Defensive against latch inference and non-onehot states; default branch still recovers to IDLE.
Removed o_data <= o_data; self-assignment	Idiomatic clock-enable form.
Parameterised FIFO_DEPTH / NUM_STREAMS / STREAM_IDX_W	Easier to retarget and read.

Functional fixes

Both fixes were verified by simulating the original and refactored RTL against packet_handler_tb.v with Icarus Verilog 12.0. The o_packetLost pulse is bit-identical at t = 235 ns, and o_valid timing matches; only o_data differs (correctly).

1. AXI-stream handshake compliance. o_data is now loaded on the DATA -> DONE transition, so it is valid in the same cycle that o_valid rises. Previously o_data was only assigned in DONE when i_ready == 1, meaning a receiver sampling on (o_valid && i_ready) would capture the previous transaction's payload (or zeros after reset) on the first cycle of the handshake.

   • Original sim, first transaction: validOut=1, dataOut=000…0  :x:
   • New sim, first transaction: validOut=1, dataOut=…5a22b2d45a22b49e42e3c71e43995b7e  :white_check_mark:

2. o_packetLost recovers after a gap. The tracker now stores the actual received seqNumber instead of unconditionally incrementing by 1. Combined with the new per-stream tracker_valid bit, the first packet of any stream is unconditionally accepted, and after a discontinuity the next sequential packet stops the pulse. Previously, once a packet was lost, every subsequent packet for that stream was incorrectly flagged as lost forever.

Verification

• iverilog -g2005-sv -Wall packet_handler.v packet_handler_tb.v — clean (no warnings).
• vvp of original vs. refactored design against the existing testbench — $monitor outputs match except for the o_data and msgLength/streamId differences described above (the second is internal-only and tagged lint_off UNUSEDSIGNAL).
• o_packetLost pulses fire at the same time on the wrong-seqNumber packet.

Known follow-ups (not in this PR)

• The FIFO uses a combinational read (fifo_data = fifo_mem[fifo_rd_ptr]), which favours distributed RAM inference. To target block RAM (BRAM) for the 256x33-bit FIFO, the FSM would need to be reworked for one-cycle read latency. Out of scope for this synthesis-quality pass.
• The output o_data is 296 bits, but {shiftReg[263:0], i_data} only carries 9 full 32-bit words = 288 bits of payload through the shift register. Packets with the maximum msgLength = 45 (37 bytes payload) would lose the last byte. Existing limitation, not regressed here.

Target

This PR targets jules-experimenting (used as the basis), as requested.