Optimize RTL for synthesis and strictly comply with Verilator linting#3
Optimize RTL for synthesis and strictly comply with Verilator linting#3RafailDD wants to merge 2 commits into
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- Updated packetTracker reset logic using SYNTHESIS guards to enable BRAM inference instead of 1024 registers. - Corrected o_data width to 296 bits in asynchronous reset and default conditions. - Added synchronous reset logic for o_packetLostReg during standard resets and non-active states. - Handled out-of-bounds indexing risk for packetTracker using index truncation on streamId (5-bits for 32 elements array). - Fixed missing EOF newline. - Masked expected UNUSEDSIGNAL warnings using Verilator lint pragmas. - Ensured all tests via cocotb pass successfully. Co-authored-by: RafailDD <123392637+RafailDD@users.noreply.github.com>
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- Add synchronous read/write Block RAM structure for `packetTracker` explicitly bound to the `SYNTHESIS` macro. - Add index address preparation in cycle 1 (`IN_W1`) and synchronous execution in cycle 2 (`IN_W2`). - Retain exact legacy simulation array behavior in non-synthesis block. - Address linting errors (`UNUSEDSIGNAL`) cleanly with pragmas. - Prevent regression out-of-bounds indexing by using correct 5-bit bounds mapping logic without hard overrides on 0 index. Co-authored-by: RafailDD <123392637+RafailDD@users.noreply.github.com>
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Optimizes the
packet_handler.vRTL to better support Block RAM synthesis and strictly comply with Verilator lint checking. Includes safety patches to array indexing and register resets.PR created automatically by Jules for task 18043434795401579258 started by @RafailDD