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feat(cute-rs): complete SM120a CuTeDSL parity, TiledCopy, BF16/NVFP4 TiledMma, and workload migrations - #1672
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nihalpasham merged 5 commits intoOct 30, 2026
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…d arch forwarders Express all three SM100a (`B200`) `*_cute` examples (`fp16_gemm_256x352_cute`, `sm100_fmha_prefill_cute`, and `sm100_mla_decode_fp16_cute`) strictly through reusable `cute-rs` operations with CuTeDSL 4.7 naming, eliminating direct `ctm_rs` instruction imports, kernel-local barrier rings, and raw tensor pointer indexing. Generated with [Devin](https://devin.ai) Co-Authored-By: Devin <158243242+devin-ai-integration[bot]@users.noreply.github.com> Signed-off-by: nihalpasham <nihalp@nvidia.com>
…TiledMma, and workload migrations Wire TiledCopy/ThrCopy (copy_g2s, copy_s2g, copy_r2s), SmemTile::local_tile/store, first-class BFloat16 in copy_g2s and ldmatrix, StridedTensor dialect lowering, and SM120 NVFP4 (E2M1 + E4M3, SF_VEC = 16) Tensor-Core TiledMma across cute-rs, mir-importer, dialect-cute, and cuda-oxide-mlir-export. Migrate all SM120a *_cute examples and Qwen workloads onto CuTeDSL-aligned cute-rs operations. Signed-off-by: nihalpasham <nihalp@nvidia.com>
…-preview/AGENTS.md Add `cuda-oxide/AGENTS.md` and update `cuda-oxide/cute-rs-preview/AGENTS.md` with the type-encoded CuTe architecture, CuTeDSL naming parity, compiler boundary, and visual documentation rules. Generated with [Devin](https://devin.ai) Co-Authored-By: Devin <158243242+devin-ai-integration[bot]@users.noreply.github.com> Signed-off-by: nihalpasham <nihalp@nvidia.com>
…cute-rs-abstractions Signed-off-by: nihalpasham <nihalp@nvidia.com>
Signed-off-by: nihalpasham <nihalp@nvidia.com>
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What This PR Does
stacked on #1671 (
feat/sm100-cute-rs-abstractions).This PR completes the SM120a (
RTX 5090)cute-rscompiler and library surface and migrates every SM120a*_cuteexample and Qwen model workload onto CuTeDSL 4.7-alignedcute-rsoperations:TiledCopy/ThrCopy(copy_g2s,copy_s2g,copy_r2s),SmemTile::{local_tile, store}, and C-fragment retiling (cute-rs)BFloat16inCuteCopyG2SOp/CuteLdmatrixOp,StridedTensordialect lowering, and vectorizedBf16Mma16x8x16(dialect-cute,mir-importer,cuda-oxide-mlir-export)Float4E2M1FN+Float8E4M3FN,SF_VEC = 16) Tensor-CoreTiledMma(Mxf4Nvf4TiledMma/Nvfp4TiledMma,CuteNvfp4MmaAtomOp)1.
TiledCopy/ThrCopy,SmemTile, and FMHA MigrationPreviously,
fmha_decode_sm120a_cuteandfmha_prefill_sm120a_cutehand-coded theSwizzle<3, 3, 3>formula (shared_offset) and wrote outputs via raw*mut u32/*mut u128pointer casts.2. First-Class
BFloat16incopy_g2s/ldmatrix&StridedTensorLoweringCuteCopyG2SOpandCuteLdmatrixOpnow acceptBFloat16directly alongsidef16andu16, removing theu16carrier cast inrope_cache_cute.StridedTensor/StridedTensorMutandBf16Mma16x8x16::{load_tiled_packed}route aligned global tile reads and writes throughTensor/TensorMut(cute.make_view+cute.zipped_divide+cute.slice+cute.copy), acceleratingqwen3_8b_cuteBF16 prefill by 2.62x (96.15 ms -> 36.66 ms).3. SM120 NVFP4 (
Float4E2M1FN+Float8E4M3FN,SF_VEC = 16) Tensor-CoreTiledMmaNvfp4TiledMma(Mxf4Nvf4TiledMma) pairsldmatrix.x4shared-memory loads and canonicalSm120ScaleAtom(E4M3x4) scale quads withCuteNvfp4MmaAtomOp, lowering tocute_nvgpu.arch.mma.SM120.block_scaled(m16n8k64.kind::mxf4nvf4.block_scale.scale_vec::4X.f32.e2m1.e2m1.f32.ue4m3):Verification & Benchmarks (
RTX 5090,sm_120a)blockscale_gemm_cute2048x2048x1024MXFP413.376 us13.376 us16.832 usfmha_prefill_sm120a17.952 us17.952 us23.200 usfmha_prefill_sm120a18.112 us17.952 us23.776 usfmha_prefill_sm120a17.952 us17.792 us22.848 usfmha_prefill_sm120a17.856 us17.888 us23.808 usfmha_decode_sm120a4.736 us4.640 us12.128 usfmha_decode_sm120a4.384 us4.480 us12.544 usqwen3_8b_cute(36L)P=32)96.15 ms36.66 msqwen3_8b_cute(36L)P=32)50.71 ms26.95 ms53.08 msqwen3_8b_cute(36L)16 tok)8.76 ms8.12 ms13.20 msscripts/smoketest.shon RTX 5090 (sm_120a): 241 / 241 examples PASSjust check&just book:fmt-check,clippy, unit tests,check-guards,check-intrinsics,doc-check, andcuda-oxide-bookbuild all PASScute-rs-previewexamples & models:elementwise_cute,swiglu_cute,nvfp4_gemv_cute,rmsnorm_cute,ffn_cute,rope_cache_cute,blockscale_gemm_cute,fmha_decode_sm120a_cute,fmha_prefill_sm120a_cute,qwen_decoder_cute, andqwen3_8b_cuteall PASS