This repository contains a UART communication system implemented in SystemVerilog (SV). The system includes both transmitter (uarttx) and receiver (uartrx) modules, along with a testbench (TB) for simulation and verification. The project is designed to handle a 9600 baud rate and 1 MHz clock frequency for UART communication.
Below is the block diagram of the UART system, showing the connections between the transmitter (utx) and receiver (rtx) modules.
uart_tx.sv: SystemVerilog code for the UART transmitter module.uart_rx.sv: SystemVerilog code for the UART receiver module.uart_top.sv: Top-level SystemVerilog code instantiating both the transmitter and receiver modules.uart_tb.sv: Testbench code for simulating and verifying the UART communication system.
- UART Transmitter (
uart_tx): Sends data serially at 9600 baud. - UART Receiver (
uart_rx): Receives data serially at 9600 baud. - Clock Generation: A custom clock is generated for UART communication using the system clock of 1 MHz to achieve the correct baud rate.
- Testbench: Simulates the UART system, verifying the functionality of the transmitter and receiver.
- Clock Frequency: 1 MHz (1,000,000 Hz)
- Baud Rate: 9600 baud
To achieve a baud rate of 9600, the clock must be divided by the following value:
Clock Division = Clock Frequency / Baud Rate = 1,000,000 / 9600 = 104.167 cycles per bit
This calculation determines the division factor for generating a UART-specific clock (uclk) from the system clock.
- SystemVerilog Simulator: You can use any SystemVerilog simulator such as QuestaSim, VCS, or Xilinx Vivado.
- SystemVerilog Compiler: To compile and simulate the code.