top_map.map

Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'top'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o top_map.ncd top.ngd top.pcf 
Target Device  : xc6slx16
Target Package : csg324
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Tue Mar 17 17:25:31 2020

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
WARNING:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
   constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
   (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
   alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
   components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
   environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.


   For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; for more information on TRCE,
   consult the Xilinx Command Line Tools User Guide "TRACE" chapter.
INFO:Timing:3284 - This timing report was generated using estimated delay 
   information.  For accurate numbers, please refer to the post Place and Route 
   timing report.
Number of Timing Constraints that were not applied: 4

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
* TS_adc_pll_m0_clkfx = PERIOD TIMEGRP "adc | SETUP       |    -4.338ns|   557.951ns|      18|       71266
  _pll_m0_clkfx" TS_sys_clk_pin * 1.3 HIGH  | HOLD        |     0.132ns|            |       0|           0
  50%                                       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_mem_ctrl_inst_ddr3_m0_memc3_infrastruc | SETUP       |    -0.770ns|    25.120ns|       1|         770
  ture_inst_mcb_drp_clk_bufg_in = PERIOD TI | HOLD        |     0.060ns|            |       0|           0
  MEGRP "mem_ctrl_inst_ddr3_m0_memc3_infras |             |            |            |        |            
  tructure_inst_mcb_drp_clk_bufg_in" TS_sys |             |            |            |        |            
  _clk_pin * 1.5625 HIGH 50%                |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_mem_ctrl_inst_ddr3_m0_memc3_infrastruc | MINPERIOD   |     0.001ns|     1.599ns|       0|           0
  ture_inst_clk_2x_180 = PERIOD TIMEGRP "me |             |            |            |        |            
  m_ctrl_inst_ddr3_m0_memc3_infrastructure_ |             |            |            |        |            
  inst_clk_2x_180" TS_sys_clk_pin * 12.5 PH |             |            |            |        |            
  ASE 0.8 ns HIGH 50%                       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_mem_ctrl_inst_ddr3_m0_memc3_infrastruc | MINPERIOD   |     0.001ns|     1.599ns|       0|           0
  ture_inst_clk_2x_0 = PERIOD TIMEGRP "mem_ |             |            |            |        |            
  ctrl_inst_ddr3_m0_memc3_infrastructure_in |             |            |            |        |            
  st_clk_2x_0" TS_sys_clk_pin * 12.5 HIGH 5 |             |            |            |        |            
  0%                                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |    12.000ns|     8.000ns|       0|           0
  pin" 50 MHz HIGH 50%                      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_mem_ctrl_inst_ddr3_m0_memc3_infrastruc | SETUP       |     1.621ns|     3.362ns|       0|           0
  ture_inst_clk0_bufg_in = PERIOD TIMEGRP " | HOLD        |     0.132ns|            |       0|           0
  mem_ctrl_inst_ddr3_m0_memc3_infrastructur | MINPERIOD   |     2.830ns|     3.570ns|       0|           0
  e_inst_clk0_bufg_in" TS_sys_clk_pin * 3.1 |             |            |            |        |            
  25 HIGH 50%                               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_grxc_clk_pin = PERIOD TIMEGRP "grxc_cl | SETUP       |     5.083ns|     2.917ns|       0|           0
  k_pin" 8 ns HIGH 50%                      | HOLD        |     0.132ns|            |       0|           0
                                            | MINPERIOD   |     4.430ns|     3.570ns|       0|           0
----------------------------------------------------------------------------------------------------------
  TS_gtxc_clk_pin = PERIOD TIMEGRP "gtxc_cl | N/A         |         N/A|         N/A|     N/A|         N/A
  k_pin" 8 ns HIGH 50%                      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths
Analyzed       |
|           Constraint          | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    |
Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|TS_sys_clk_pin                 |     20.000ns|      8.000ns|    725.336ns|            0|           19|            0|   
    33425|
| TS_adc_pll_m0_clkfx           |     15.385ns|    557.951ns|          N/A|           18|            0|         3920|   
        0|
| TS_mem_ctrl_inst_ddr3_m0_memc3|     12.800ns|     25.120ns|          N/A|            1|            0|        24471|   
        0|
| _infrastructure_inst_mcb_drp_c|             |             |             |             |             |             |   
         |
| lk_bufg_in                    |             |             |             |             |             |             |   
         |
| TS_mem_ctrl_inst_ddr3_m0_memc3|      1.600ns|      1.599ns|          N/A|            0|            0|            0|   
        0|
| _infrastructure_inst_clk_2x_18|             |             |             |             |             |             |   
         |
| 0                             |             |             |             |             |             |             |   
         |
| TS_mem_ctrl_inst_ddr3_m0_memc3|      1.600ns|      1.599ns|          N/A|            0|            0|            0|   
        0|
| _infrastructure_inst_clk_2x_0 |             |             |             |             |             |             |   
         |
| TS_mem_ctrl_inst_ddr3_m0_memc3|      6.400ns|      3.570ns|          N/A|            0|            0|         5034|   
        0|
| _infrastructure_inst_clk0_bufg|             |             |             |             |             |             |   
         |
| _in                           |             |             |             |             |             |             |   
         |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+

2 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 11 secs 
Total CPU  time at the beginning of Placer: 11 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:ad62d82c) REAL time: 12 secs 

Phase 2.7  Design Feasibility Check
WARNING:Place:1206 - This design contains a global buffer instance,
   <adc_pll_m0/clkout1_buf>, driving the net, <ad9238_clk_ch0_OBUF>, that is
   driving the following (first 30) non-clock load pins off chip.
   < PIN: ad9238_clk_ch0.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was
   applied on COMP.PIN <adc_pll_m0/clkout1_buf.O> allowing your design to
   continue. This constraint disables all clock placer rules related to the
   specified COMP.PIN.
WARNING:Place:1137 - This design is not guaranteed to be routable! This design
   contains a global buffer instance, <adc_pll_m0/clkout1_buf>, driving the net,
   <ad9238_clk_ch0_OBUF>, that is driving the following (first 30) non-clock
   load pins.
   < PIN: ad9238_clk_ch0.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. Please pay extra attention to the timing and routing of this path to
   ensure the design goals are met. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
   <adc_pll_m0/clkout1_buf.O> allowing your design to continue. This constraint
   disables all clock placer rules related to the specified COMP.PIN.
Phase 2.7  Design Feasibility Check (Checksum:ad62d82c) REAL time: 12 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:ad62d82c) REAL time: 12 secs 

Phase 4.2  Initial Placement for Architecture Specific Features

Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:f2d10a8f) REAL time: 17 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:f2d10a8f) REAL time: 17 secs 

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:f2d10a8f) REAL time: 17 secs 

Phase 7.3  Local Placement Optimization
Phase 7.3  Local Placement Optimization (Checksum:f2d10a8f) REAL time: 17 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:f2d10a8f) REAL time: 17 secs 

Phase 9.8  Global Placement
..................................
.........................................................................
.................................................................................................................................
..........................................................................................................................................................................................
......................................
Phase 9.8  Global Placement (Checksum:40eb5a9f) REAL time: 47 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:40eb5a9f) REAL time: 47 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:c75f04df) REAL time: 54 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:c75f04df) REAL time: 55 secs 

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:887e5444) REAL time: 55 secs 

Total REAL time to Placer completion: 55 secs 
Total CPU  time to Placer completion: 55 secs 
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    4
Slice Logic Utilization:
  Number of Slice Registers:                 3,616 out of  18,224   19%
    Number used as Flip Flops:               3,605
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:               11
  Number of Slice LUTs:                      3,875 out of   9,112   42%
    Number used as logic:                    3,741 out of   9,112   41%
      Number using O6 output only:           2,181
      Number using O5 output only:             335
      Number using O5 and O6:                1,225
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   2,176    0%
    Number used exclusively as route-thrus:    134
      Number with same-slice register load:     70
      Number with same-slice carry load:        63
      Number with other load:                    1

Slice Logic Distribution:
  Number of occupied Slices:                 1,463 out of   2,278   64%
  Number of MUXCYs used:                     1,664 out of   4,556   36%
  Number of LUT Flip Flop pairs used:        4,782
    Number with an unused Flip Flop:         1,677 out of   4,782   35%
    Number with an unused LUT:                 907 out of   4,782   18%
    Number of fully used LUT-FF pairs:       2,198 out of   4,782   45%
    Number of unique control sets:             175
    Number of slice register sites lost
      to control set restrictions:             323 out of  18,224    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        90 out of     232   38%
    Number of LOCed IOBs:                       90 out of      90  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         3 out of      32    9%
  Number of RAMB8BWERs:                          1 out of      64    1%
  Number of BUFIO2/BUFIO2_2CLKs:                 2 out of      32    6%
    Number used as BUFIO2s:                      2
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             1 out of      32    3%
    Number used as BUFIO2FBs:                    1
    Number used as BUFIO2FB_2CLKs:               0
  Number of BUFG/BUFGMUXs:                       5 out of      16   31%
    Number used as BUFGs:                        4
    Number used as BUFGMUX:                      1
  Number of DCM/DCM_CLKGENs:                     1 out of       4   25%
    Number used as DCMs:                         1
    Number used as DCM_CLKGENs:                  0
  Number of ILOGIC2/ISERDES2s:                   0 out of     248    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:        24 out of     248    9%
    Number used as IODELAY2s:                    0
    Number used as IODRP2s:                      2
    Number used as IODRP2_MCBs:                 22
  Number of OLOGIC2/OSERDES2s:                  47 out of     248   18%
    Number used as OLOGIC2s:                     0
    Number used as OSERDES2s:                   47
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         1 out of       4   25%
  Number of DSP48A1s:                            0 out of      32    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                1 out of       2   50%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       2   50%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                3.67

Peak Memory Usage:  638 MB
Total REAL time to MAP completion:  58 secs 
Total CPU time to MAP completion:   58 secs 

Mapping completed.
See MAP report file "top_map.mrp" for details.