more about cp

Author: vxpm

book.toml

@@ -13,4 +13,4 @@ title = "cubenotes"
 additional-css = ["theme/pagetoc.css", "theme/custom.css"]
 additional-js = ["theme/pagetoc.js", "theme/custom.js"]
 smart-punctuation = true
-git-repository-url = "https://github.com/vxpm/psxnotes"
+git-repository-url = "https://github.com/vxpm/cubenotes"

src/command-processor.md

@@ -3,7 +3,43 @@
 The command processor is responsible for fetching and processing commands generated by the CPU from
 a FIFO.
 
-## CP FIFO
+## Registers
+
+> [!NOTE]
+> The FIFO registers are described in the FIFO section next.
+
+### CP Status (`0x0C00_0000`, 2 bytes)
+
+| Bits  | Name                    | Description                     |
+| ----- | ----------------------- | ------------------------------- |
+| 0     | CP FIFO Overflow        | [Watermark logic](#linked-mode) |
+| 1     | CP FIFO Underflow       | [Watermark logic](#linked-mode) |
+| 2     | CP is idle for reading  |                                 |
+| 3     | CP is idle for commands |                                 |
+| 4     | BP Interrupt            |                                 |
+| 5..16 |                         | Unused                          |
+
+### CP Control (`0x0C00_0002`, 2 bytes)
+
+| Bits  | Name                        | Description                                     |
+| ----- | --------------------------- | ----------------------------------------------- |
+| 0     | CP FIFO Read Enable         | Whether the CP will read commands from the FIFO |
+| 1     | BP Enable                   |                                                 |
+| 2     | CP FIFO Overflow IRQ Enable |                                                 |
+| 3     | CP FIFO Overflow IRQ Enable |                                                 |
+| 4     | CP FIFO Linked Mode         | Controls the [FIFO mode](#fifo). On reset is 1  |
+| 5     | BP IRQ Enable               |                                                 |
+| 6..16 |                             | Unused                                          |
+
+### CP Clear (`0x0C00_0004`, 2 bytes, write only)
+
+| Bits  | Name                    | Description                   |
+| ----- | ----------------------- | ----------------------------- |
+| 0     | Clear CP FIFO Overflow  | Write 1 to clear status bit 0 |
+| 1     | Clear CP FIFO Underflow | Write 1 to clear status bit 1 |
+| 2..16 |                         | Unused                        |
+
+## FIFO
 
 The command processor has a FIFO mechanism that builds and consumes ring buffers of commands in RAM,
 controlled by a bunch of registers:

src/introduction.md

@@ -24,3 +24,5 @@ Currently, it is not sufficient on it's own - please see [the resources page](re
   e.g. `0xDEAD_BEEF`
 - Likewise, binary values are always prefixed with `0b` and separated with an underline every 4
   digits, e.g. `0b1111_0000_1010_0011`
+- Every MMIO register is both readable and writable unless stated otherwise
+- Every bit flag is 0 for `false` and 1 for `true` unless stated otherwise

src/processor-interface.md

@@ -6,7 +6,7 @@ The processor interface is responsible for connecting the CPU to the Flipper.
 
 The PI receives interrupt requests from Flipper and passes them along to the CPU.
 
-## PI FIFO
+## FIFO
 
 Within the PI exists a FIFO mechanism that catches burst writes[^wgp] to `0x0C00_8000` and writes
 them to a ring buffer in memory. It's controlled by three registers: