drl acc int sign-extend fix

Author: NikhilRout

hw/rtl/tcu/VX_tcu_fedp_drl.sv

@@ -95,6 +95,7 @@ module VX_tcu_fedp_drl #(
         .N(TCK+1)
     ) csa_acc (
         .sigsIn   (pipe_aln_sigs),
+        .fmt_sel  (pipe_fmt_sel),
         .sigOut   (acc_sig),
         .signOuts (sigs_sign)
     );

hw/rtl/tcu/drl/VX_tcu_drl_acc.sv

@@ -18,13 +18,14 @@ module VX_tcu_drl_acc #(
     parameter W = 25+$clog2(N)+1
 ) (
     input  wire [N-1:0][24:0] sigsIn,
+    input  wire fmt_sel,
     output logic [W-1:0] sigOut,
     output logic [N-2:0] signOuts
 );
-    // Sign-extend addends to W bits
+    // Sign-extend fp significands to W bits
     wire [N-1:0][W-1:0] sigsIn_ext;
     for (genvar i = 0; i < N; i++) begin : g_ext_sign
-        assign sigsIn_ext[i] = {{(W-25){sigsIn[i][24]}}, sigsIn[i]};
+        assign sigsIn_ext[i] = fmt_sel ? {{(W-25){1'b0}}, sigsIn[i]} : {{(W-25){sigsIn[i][24]}}, sigsIn[i]};
     end
 
     //Carry-Save-Adder based significand accumulation

hw/rtl/tcu/drl/VX_tcu_drl_norm_round.sv

@@ -62,15 +62,15 @@ module VX_tcu_drl_norm_round #(
 
     //Final INT addition
     wire [6:0] ext_acc_int = 7'($signed(acc_sig[25+$clog2(N):25]));
-    wire [N-1:0][6:0] ext_signs;
+    wire [N-2:0][6:0] ext_signs;
     for (genvar i = 0; i < N-1; i++) begin : g_sign_ext
         assign ext_signs[i] = 7'($signed(sigSigns[i]));
     end
-    assign ext_signs[N-1] = 7'd0; //($signed(acc_sig[25+$clog2(N)-1]));
+
     wire [6:0] int_hi;
 
     VX_csa_tree #(
-        .N (N+2),
+        .N (N+1),
         .W (7),
         .S (7)
     ) int_adder (