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Merge branch 'bug_fixes' of https://github.com/vortexgpgpu/vortex into bug_fixes
2 parents ae446a4 + 6ec856d commit a06608c

5 files changed

Lines changed: 171 additions & 7 deletions

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‎hw/rtl/core/VX_dispatch.sv‎

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_dispatch import VX_gpu_pkg::*; #(
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parameter `STRING INSTANCE_ID = "",
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parameter ISSUE_ID = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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output wire [NUM_EX_UNITS-1:0][PERF_CTR_BITS-1:0] perf_stalls,
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output wire [NUM_EX_UNITS-1:0][PERF_CTR_BITS-1:0] perf_instrs,
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`endif
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// inputs
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VX_operands_if.slave operands_if,
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// outputs
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VX_dispatch_if.master dispatch_if [NUM_EX_UNITS]
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);
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`UNUSED_SPARAM (INSTANCE_ID)
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`UNUSED_PARAM (ISSUE_ID)
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36+
localparam OUT_DATAW = $bits(dispatch_t);
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wire [NUM_EX_UNITS-1:0] operands_ready_in;
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assign operands_if.ready = operands_ready_in[operands_if.data.ex_type];
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41+
for (genvar i = 0; i < NUM_EX_UNITS; ++i) begin : g_buffers
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VX_elastic_buffer #(
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.DATAW (OUT_DATAW),
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.SIZE (2),
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.OUT_REG (1)
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) buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (operands_if.valid && (operands_if.data.ex_type == EX_BITS'(i))),
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.ready_in (operands_ready_in[i]),
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.data_in ({
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operands_if.data.uuid,
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operands_if.data.wis,
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operands_if.data.sid,
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operands_if.data.tmask,
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operands_if.data.PC,
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operands_if.data.wb,
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operands_if.data.wr_xregs,
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operands_if.data.rd,
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operands_if.data.op_type,
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operands_if.data.op_args,
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operands_if.data.rs1_data,
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operands_if.data.rs2_data,
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operands_if.data.rs3_data,
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operands_if.data.sop,
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operands_if.data.eop
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}),
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.data_out (dispatch_if[i].data),
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.valid_out (dispatch_if[i].valid),
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.ready_out (dispatch_if[i].ready)
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);
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end
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`ifdef PERF_ENABLE
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reg [NUM_EX_UNITS-1:0][PERF_CTR_BITS-1:0] perf_stalls_r;
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reg [NUM_EX_UNITS-1:0][PERF_CTR_BITS-1:0] perf_instrs_r;
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wire operands_if_fire = operands_if.valid && operands_if.ready;
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wire operands_if_stall = operands_if.valid && ~operands_if.ready;
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for (genvar i = 0; i < NUM_EX_UNITS; ++i) begin : g_perf_stalls
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always @(posedge clk) begin
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if (reset) begin
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perf_stalls_r[i] <= '0;
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perf_instrs_r[i] <= '0;
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end else begin
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perf_stalls_r[i] <= perf_stalls_r[i] + PERF_CTR_BITS'(operands_if_stall && operands_if.data.ex_type == EX_BITS'(i));
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perf_instrs_r[i] <= perf_instrs_r[i] + PERF_CTR_BITS'(operands_if_fire && operands_if.data.ex_type == EX_BITS'(i) && operands_if.data.eop);
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end
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end
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assign perf_stalls[i] = perf_stalls_r[i];
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assign perf_instrs[i] = perf_instrs_r[i];
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end
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`endif
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endmodule

‎hw/rtl/core/VX_schedule.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -487,7 +487,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
487487
end
488488
end
489489

490-
`RUNTIME_ASSERT(timeout_ctr < STALL_TIMEOUT, ("*** %s timeout: stalled_warps=%b", INSTANCE_ID, stalled_warps))
490+
`RUNTIME_ASSERT(timeout_ctr < STALL_TIMEOUT, ("*** %s timeout: active_warps=%b stalled_warps=%b pc0=0x%0h", INSTANCE_ID, active_warps, stalled_warps, to_fullPC(warp_pcs[0])))
491491

492492
`ifdef PERF_ENABLE
493493
reg [PERF_CTR_BITS-1:0] perf_sched_idles;

‎sim/simx/cluster.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ class Cluster : public SimObject<Cluster> {
3535
struct AsyncClusterBarrier {
3636
static constexpr uint32_t MAX_CORES = 32;
3737

38-
CoreMask arrived_cores;
38+
CoreMask arrived_cores;
3939
CoreMask waiting_cores;
4040
uint32_t arrived_count;
4141
uint32_t expect_cores;
@@ -99,6 +99,9 @@ class Cluster : public SimObject<Cluster> {
9999

100100
uint32_t async_barrier_arrive(uint32_t bar_id, uint32_t count, uint32_t core_id);
101101
bool async_barrier_wait(uint32_t bar_id, uint32_t token, uint32_t core_id);
102+
uint32_t async_barrier_token(uint32_t bar_id) const {
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return async_barriers_.at(bar_id).generation;
104+
}
102105

103106
PerfStats perf_stats() const;
104107

‎sim/simx/emulator.cpp‎

Lines changed: 43 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,7 @@ Emulator::Emulator(const Arch &arch, const DCRS &dcrs, Core* core)
8080
, barriers_(arch.num_barriers(), 0)
8181
, ipdom_size_(arch.num_threads()-1)
8282
, async_barriers_(arch.num_barriers())
83+
, cluster_async_barriers_(arch.num_barriers())
8384
#ifdef EXT_TCU_ENABLE
8485
, tensor_unit_(core->tensor_unit())
8586
#endif
@@ -118,6 +119,10 @@ void Emulator::reset() {
118119
async_bar.reset_for_next_gen();
119120
}
120121

122+
for (auto& async_bar : cluster_async_barriers_) {
123+
async_bar.reset();
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}
125+
121126
#ifdef EXT_V_ENABLE
122127
vec_unit_->reset();
123128
#endif
@@ -291,7 +296,43 @@ uint32_t Emulator::barrier_arrive(uint32_t bar_id, uint32_t count, uint32_t wid)
291296
uint32_t bar_idx = bar_id & 0x7fffffff;
292297

293298
if (is_cluster) {
294-
return core_->socket()->async_barrier_arrive(bar_idx, count, core_->id());
299+
auto& b = cluster_async_barriers_.at(bar_idx);
300+
301+
if (b.expect_cores == 0) {
302+
b.expect_cores = count;
303+
} else {
304+
assert(b.expect_cores == count);
305+
}
306+
307+
uint32_t gen = core_->socket()->cluster()->async_barrier_token(bar_idx);
308+
if (b.token_valid && gen > b.token) {
309+
b.arrived_warps.reset();
310+
b.core_arrived = false;
311+
b.token_valid = false;
312+
b.token = 0;
313+
}
314+
315+
if (!b.token_valid) {
316+
b.token = gen;
317+
b.token_valid = true;
318+
} else {
319+
assert(gen == b.token);
320+
}
321+
322+
uint32_t token = b.token;
323+
324+
// Record warp arrival for this core.
325+
b.arrived_warps.set(wid);
326+
327+
// Count a core's arrival only once all its currently-active warps have arrived.
328+
if (!b.core_arrived && ((b.arrived_warps & active_warps_) == active_warps_)) {
329+
uint32_t token2 = core_->socket()->async_barrier_arrive(bar_idx, count, core_->id());
330+
assert(token2 == token);
331+
(void)token2;
332+
b.core_arrived = true;
333+
}
334+
335+
return token;
295336
}
296337

297338
auto& b = async_barriers_.at(bar_idx);
@@ -306,7 +347,6 @@ uint32_t Emulator::barrier_arrive(uint32_t bar_id, uint32_t count, uint32_t wid)
306347

307348
// If arrived in the same generation before, skip but still return token
308349
if (b.arrived_mask.test(wid)) {
309-
std::cout << " >> ARRIVE_DUP warp=" << wid << " (already arrived this gen)\n";
310350
return token;
311351
}
312352

@@ -350,7 +390,6 @@ bool Emulator::barrier_wait(uint32_t bar_id, uint32_t token, uint32_t wid) {
350390
stalled_warps_.set(wid);
351391
return false;
352392
}
353-
// stalled_warps_.reset(wid);
354393
return true;
355394
}
356395

@@ -362,7 +401,7 @@ bool Emulator::barrier_wait(uint32_t bar_id, uint32_t token, uint32_t wid) {
362401
uint32_t desired_gen = token + 1;
363402

364403
if (b.generation >= desired_gen) {
365-
404+
366405

367406
b.waiting_mask.reset(wid);
368407
// stalled_warps_.reset(wid);

‎sim/simx/emulator.h‎

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,32 @@ class Emulator {
201201

202202
std::vector<AsyncBarrier> async_barriers_;
203203

204+
struct ClusterAsyncBarrier {
205+
WarpMask arrived_warps;
206+
uint32_t expect_cores;
207+
uint32_t token;
208+
bool token_valid;
209+
bool core_arrived;
210+
211+
ClusterAsyncBarrier()
212+
: expect_cores(0)
213+
, token(0)
214+
, token_valid(false)
215+
, core_arrived(false) {
216+
arrived_warps.reset();
217+
}
218+
219+
void reset() {
220+
arrived_warps.reset();
221+
expect_cores = 0;
222+
token = 0;
223+
token_valid = false;
224+
core_arrived = false;
225+
}
226+
};
227+
228+
std::vector<ClusterAsyncBarrier> cluster_async_barriers_;
229+
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205231
#ifdef EXT_TCU_ENABLE
206232
TensorUnit::Ptr tensor_unit_;
@@ -215,4 +241,4 @@ std::vector<AsyncBarrier> async_barriers_;
215241

216242
}
217243

218-
#endif
244+
#endif

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