The compiler team would like to ask the library team for consensus regarding whether or not library team is willing to accept a promotion of RISC-V 32bit ESP-IDF targets, riscv32imc-esp-espidf, riscv32imac-esp-espidf, and riscv32imafc-esp-espidf to tier 2 with limited std support:
core, alloc, and panic_abort are fully implemented.
std is fully implemented as well, except for support for processes and signals, which are stubbed out.
We do understand that not implementing processes (and therefore signals) is a bit controversial, but with that said, an MCU target cannot feasibly implement those, as often there is just no notion of “multiple processes” there (as is the case with ESP-IDF).
So we do believe we cannot possibly support processes and signals indeed, and thus we fall in the same category as other Tier 2 targets, like wasm, where neither processes, nor even other core aspects of the Standard Library, like multi-threading, BSD sockets, or even mutexes are implemented.
Prior related library team decisions
armv7a-vex-v5 implements as much of the standard library as is possible using only public VEX SDK functions.
This includes:
std::time, not including SystemTime as the SDK does not provide absolute time information.
std::io, including std::io::stdin() and std::io::stdout, but not std::stderr(), as stderr does not exist on this platform.
std::fs, with the exception of directory reading and file deletion, due to public SDK limitations.
- modules which do not need to interact with the OS beyond allocation,
such as std::collections, std::hash, std::future, std::sync, etc.
Notable modules which are not implemented include:
std::process
std::thread
std::net
There, the library team consensus was
We discussed this in the libs meeting today. While this is indeed missing a lot of what would normally be present in a std target, it does at least have the basics down like support for Instant (which is one of the biggest issues with wasm32-unknown-unknown). We're happy for this to be accepted at tier 3 but would likely reject it for higher tiers.
#131530 (comment)
From the target tier policy document:
Tier 3:
std for targets with an operating system or equivalent layer of system-provided functionality), but may leave some code unimplemented (either unavailable or stubbed out as appropriate), whether because the target makes it impossible to implement or challenging to implement.
Tier 2:
Tier 2 targets must not leave any significant portions of core or the standard library unimplemented or stubbed out, unless they cannot possibly be supported on the target.
The libs team is happy to have as a tier 3 target but would block it from any higher tier.
More context
@rustbot label: I-libs-nominated T-libs
The compiler team would like to ask the library team for consensus regarding whether or not library team is willing to accept a promotion of RISC-V 32bit ESP-IDF targets,
riscv32imc-esp-espidf,riscv32imac-esp-espidf, andriscv32imafc-esp-espidfto tier 2 with limited std support:Prior related library team decisions
armv7a-vex-v5in Addarmv7a-vex-v5tier three target #131530 where that targetThere, the library team consensus was
riscv32im-risc0-zkvm-elftarget: Status of the riscv32im-risc0-zkvm-elf target #135376 (comment)More context
@rustbot label: I-libs-nominated T-libs