Clean up assembly code a little

Add some extra comments, and replace an ldmia with a pop.

Author: thejpster

aarch32-rt/src/arch_v4/abort.rs

@@ -34,7 +34,7 @@ core::arch::global_asm!(
         pop     {{ r0-r4, r12 }}          // restore preserved registers, dummy value, and alignment amount
         add     sp, r12                   // restore SP alignment using R12
         pop     {{ r12 }}                 // restore SPSR using R12
-        msr     spsr_cxsf, r12            //
+        msr     spsr, r12                 //
         pop     {{ r12 }}                 // restore R12
         movs    pc, lr                    // return from exception
     .size _asm_default_data_abort_handler, . - _asm_default_data_abort_handler
@@ -75,7 +75,7 @@ core::arch::global_asm!(
         pop     {{ r0-r4, r12 }}          // restore preserved registers, dummy value, and alignment amount
         add     sp, r12                   // restore SP alignment using R12
         pop     {{ r12 }}                 // restore SPSR using R12
-        msr     spsr_cxsf, r12            //
+        msr     spsr, r12                 //
         pop     {{ r12 }}                 // restore R12
         movs    pc, lr                    // return from exception
     .size _asm_default_prefetch_abort_handler, . - _asm_default_prefetch_abort_handler

aarch32-rt/src/arch_v4/interrupt.rs

@@ -35,9 +35,9 @@ core::arch::global_asm!(
         pop     {{ r0-r3, r12, lr }}      // restore alignment amount (in LR) and preserved registers
         add     sp, lr                    // restore SP alignment using LR
         msr     cpsr_c, {irq_mode}        // switch back to IRQ mode (with IRQ masked)
-        ldmia   sp!, {{ lr }}             // load and restore SPSR using LR
+        pop     {{ lr }}                  // load and restore SPSR using LR
         msr     spsr, lr                  //
-        ldmfd   sp!, {{ pc }}^            // return from exception
+        ldmfd   sp!, {{ pc }}^            // return from exception (^ => restore SPSR to CPSR)
     .size _asm_default_irq_handler, . - _asm_default_irq_handler
     "#,
     // sys mode with IRQ masked

aarch32-rt/src/arch_v4/svc.rs

@@ -46,8 +46,8 @@ core::arch::global_asm!(
         mov     r0, lr                    // replace R0 with return value from _svc_handler
         add     sp, r12                   // restore SP alignment using R12
         pop     {{ lr }}                  // restore SPSR using LR
-        msr     spsr_cxsf, lr             //
-        ldmfd   sp!, {{ r12, pc }}^       // restore R12 and return from exception
+        msr     spsr, lr                  //
+        ldmfd   sp!, {{ r12, pc }}^       // restore R12 and return from exception (^ => restore SPSR to CPSR)
     .size _asm_default_svc_handler, . - _asm_default_svc_handler
     "#,
     t_bit = const { crate::Cpsr::new_with_raw_value(0).with_t(true).raw_value() },

aarch32-rt/src/arch_v4/undefined.rs

@@ -39,9 +39,9 @@ core::arch::global_asm!(
         pop     {{ r0-r4, r12 }}          // restore preserved registers, dummy value, and alignment amount
         add     sp, r12                   // restore SP alignment using R12
         pop     {{ r12 }}                 // restore SPSR using R12
-        msr     spsr_cxsf, r12            //
+        msr     spsr, r12                 //
         pop     {{ r12 }}                 // restore R12
-        movs    pc, lr                    // return from exception
+        movs    pc, lr                    // return from exception (movs => restore SPSR to CPSR)
     .size _asm_default_undefined_handler, . - _asm_default_undefined_handler
     "#,
     t_bit = const { crate::Cpsr::new_with_raw_value(0).with_t(true).raw_value() },