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RISC-V MultiPrecision Processor Core

License Verilog Status Verification

A repository for RISC-V Processor Design, bridging the gap from fundamental theory to advanced implementation. It features both Single-Cycle (Golden Reference) and 5-Stage Pipelined (High-Performance) architectures, providing a complete learning path for Computer Architecture students and engineers.

🎓 New to this? Start with our Beginner's Guide for a jargon-free introduction.

🌟 Key Features

  • Evolutionary Learning Path: Step-by-step progression from simple 32-bit (rv32i_SingleCycle) & 64-bit (rv64i_SingleCycle) Single-Cycle designs to a robust 5-Stage Pipelined architecture.
  • ASIC Proven: The Pipelined Core has been physically hardened using the Sky130 node and LibreLane (OpenLane) flow, continuing the journey from RTL to GDSII.
  • Multi-Precision Support: Full source code for both 32-bit and 64-bit data paths.
  • Advanced Features:
    • Pipelining: 5-stage design (IF, ID, EX, MEM, WB) with Hazard Detection and Forwarding.
    • Harvard Architecture: Separate Instruction and Data memories.
    • GPIO: Standardized Memory-mapped I/O across all architectures (32-bit, 64-bit, and Pipelined).
  • Synthesizable: Written in SystemVerilog, optimized for FPGAs (Artix-7, Cyclone V).
  • Modular: Clean separation of Data Path, Control, and Hazards.

🏗️ High-Level Architecture

The processor executes instructions in a single clock cycle: Fetch $\rightarrow$ Decode $\rightarrow$ Execute $\rightarrow$ Memory $\rightarrow$ Writeback.

graph TD
    %% Styling
    classDef module fill:#e1f5fe,stroke:#01579b,stroke-width:2px;
    classDef memory fill:#fff3e0,stroke:#e65100,stroke-width:2px;
    
    subgraph Processor ["RISC-V Processor Core"]
        PC[Program Counter]:::module
        Control[Control Unit]:::module
        RegFile[Register File]:::module
        ALU[ALU]:::module
        ImmGen[Immediate Gen]:::module
        
        PC --> IM
        IM --> Control
        IM --> RegFile
        IM --> ImmGen
        
        RegFile --> ALU
        ImmGen --> ALU
        Control --> ALU
        Control --> RegFile
        Control --> DM
    end
    
    subgraph Memory ["Memory Subsystem"]
        IM[Instruction Memory]:::memory
        DM[Data Memory]:::memory
    end

    ALU --> DM
    DM --> RegFile
    ALU --> RegFile
Loading

For a deep dive into the internal modules, signal flow, and decoder logic, implementation details, please read our Architecture Documentation:

📂 Repository Structure

.
├── rv32i_SingleCycle/    # [Step 1] 32-bit Single-Cycle (Golden Reference)
│   └── src_modules/        # SystemVerilog source files
│       ├── CPU.sv                    # Top-level processor
│       ├── ALU.sv                    # Arithmetic Logic Unit
│       ├── Register_File.sv          # 32 x 32-bit registers
│       ├── Control_Unit.sv           # Instruction decoder
│       ├── Immediate_Generator.sv    # Immediate extraction
│       └── ...                       # Other modules
│
├── rv64i_SingleCycle/    # [Step 2] 64-bit Single-Cycle (Advanced Data Width)
│   └── src_modules/        # Same structure as rv32i, 64-bit data paths
│
├── rv32i_pipelined/        # [Step 3] 32-bit 5-Stage Pipelined (High Performance)
│   ├── src_modules/
│   │   ├── CPU.sv                    # Top-level (with pipeline structure)
│   │   ├── FPGA_Wrapper.sv           # FPGA synthesis wrapper
│   │   ├── ALU.sv                    # [REUSED] Identical to SingleCycle
│   │   ├── Register_File.sv          # [REUSED] Identical to SingleCycle
│   │   ├── Immediate_Generator.sv    # [REUSED] Identical to SingleCycle
│   │   ├── ALU_Decoder.sv            # [REUSED] Identical to SingleCycle
│   │   ├── Main_Decoder.sv           # [ADAPTED] LUI uses ALU path
│   │   ├── Control_Unit.sv           # [ADAPTED] No branch resolution
│   │   ├── Program_Counter.sv        # [ADAPTED] Added stall support
│   │   ├── IF_ID_Reg.sv              # [NEW] Pipeline register
│   │   ├── ID_EX_Reg.sv              # [NEW] Pipeline register
│   │   ├── EX_MEM_Reg.sv             # [NEW] Pipeline register
│   │   ├── MEM_WB_Reg.sv             # [NEW] Pipeline register
│   │   ├── Hazard_Unit.sv            # [NEW] Stall/Flush detection
│   │   ├── Forwarding_Unit.sv        # [NEW] Data forwarding
│   │   └── Mux3.sv                   # [NEW] 3-to-1 multiplexer
│   ├── tb/                           # Testbenches
│   └── programs/                     # Test programs (.hex)
│
├── asic/rv32i_pipelined/ # [Step 4] ASIC Implementation (Sky130)
│   ├── config_linux.json     # OpenLane Configuration
│   ├── reports/final/        # Final GDSII, LEF, Netlist, SPEF
│   └── runs/                 # Run directories (gitignored)
│
├── docs/                   # Learning Center
│   ├── ARCHITECTURE.md                 # Architecture Theory
│   ├── TRANSITION_GUIDE.md             # SingleCycle → Pipeline Evolution
│   ├── RV32I_WALKTHROUGH.md            # Single-Cycle Guide
│   ├── RV32I_PIPELINED_WALKTHROUGH.md  # Pipeline & Hazard Guide
│   └── GETTING_STARTED.md              # Simulation Setup
│
├── CONTRIBUTING.md         # Guidelines for contributors
├── LICENSE                 # MIT License
└── README.md               # Project Entry Point

🔄 Module Reuse Summary

Module SingleCycle Pipelined Status
ALU ✅ ✅ REUSED (identical)
Register_File ✅ ✅ REUSED (identical)
Immediate_Generator ✅ ✅ REUSED (identical)
Main_Decoder ✅ ✅ ADAPTED (LUI via ALU)
ALU_Decoder ✅ ✅ REUSED (identical)
Control_Unit ✅ ✅ ADAPTED (no branch logic)
Program_Counter ✅ ✅ ADAPTED (stall support)
Pipeline Registers ❌ ✅ NEW
Hazard_Unit ❌ ✅ NEW
Forwarding_Unit ❌ ✅ NEW

📖 See TRANSITION_GUIDE.md for detailed explanation of every change.

🚀 Usage & Simulation

This processor is designed to be simulator-agnostic. It works out-of-the-box with Xilinx Vivado, ModelSim, and Icarus Verilog.

Quick Start (Vivado/ModelSim)

  1. Choose your Core:
    • Single-Cycle (32-bit): Add all files from rv32i_SingleCycle/src_modules.
    • Pipelined (32-bit): Add all files from rv32i_pipelined/src_modules.
  2. Set Top Module:
    • Set CPU.sv as the top module.
  3. Simulation:
    • Create a testbench instantiating CPU.
    • Run Behavioral Simulation.

For detailed step-by-step instructions, see the Getting Started Guide.

🔧 Technical Specifications

Feature Single-Cycle RV32I Single-Cycle RV64I Pipelined RV32I
Pipeline Stages 1 1 5 (IF/ID/EX/MEM/WB)
Throughput 1 Inst / Cycle 1 Inst / Cycle ~1 Inst / Cycle (Higher Freq)
Hazard Handling None Needed None Needed Forwarding & Stalling
Registers 32 x 32-bit 32 x 64-bit 32 x 32-bit
Max Freq (Artix-7) ~70 MHz ~60 MHz ~120 MHz+
Max Freq (Sky130) N/A N/A 31.7 MHz (Signoff)
Area (Sky130) N/A N/A 0.37 mm²

🤝 Community & Contribution

We welcome contributions! Whether it's adding support for the M extension, optimizing the ALU, or improving documentation. Please review CONTRIBUTING.md before submitting a Pull Request.

� License

This project is open-source and available under the MIT License.