From d924354cb825058999deb3760eb0f0effe91ee70 Mon Sep 17 00:00:00 2001
From: Nikhita Nadgauda <nnadgaud@qti.qualcomm.com>
Date: Wed, 19 Aug 2026 21:53:17 -0700
Subject: [PATCH] Add ARM target for PDP Cortex-M7 bring-up

Add ARM as a target alongside aarch64 for Cortex-M7.
Counterpart to the libqemu-side arm build-target enablement; needed
so qbox can select and load a 32-bit ARM QemuInstance for PDP
Cortex-M7 bring-up.

Signed-off-by: Nikhita Nadgauda <nnadgaud@qti.qualcomm.com>
---
 .../common/include/libqemu-cxx/target_info.h           |  1 +
 qemu-components/common/include/qemu-instance.h         |  2 ++
 qemu-components/common/src/libqemu-cxx/target-info.cc  | 10 ++++++++++
 3 files changed, 13 insertions(+)

diff --git a/qemu-components/common/include/libqemu-cxx/target_info.h b/qemu-components/common/include/libqemu-cxx/target_info.h
index 7d81b0e9..cd63b4e9 100644
--- a/qemu-components/common/include/libqemu-cxx/target_info.h
+++ b/qemu-components/common/include/libqemu-cxx/target_info.h
@@ -12,6 +12,7 @@ namespace qemu {
 
 enum Target {
     AARCH64,
+    ARM,
     RISCV64,
     RISCV32,
     MICROBLAZE,
diff --git a/qemu-components/common/include/qemu-instance.h b/qemu-components/common/include/qemu-instance.h
index ed006a27..14b160d5 100644
--- a/qemu-components/common/include/qemu-instance.h
+++ b/qemu-components/common/include/qemu-instance.h
@@ -292,6 +292,8 @@ class QemuInstance : public sc_core::sc_module
     {
         if (s == "AARCH64") {
             return QemuInstance::Target::AARCH64;
+        } else if (s == "ARM") {
+            return QemuInstance::Target::ARM;
         } else if (s == "RISCV64") {
             return QemuInstance::Target::RISCV64;
         } else if (s == "RISCV32") {
diff --git a/qemu-components/common/src/libqemu-cxx/target-info.cc b/qemu-components/common/src/libqemu-cxx/target-info.cc
index 85cda0c2..f4a43082 100644
--- a/qemu-components/common/src/libqemu-cxx/target-info.cc
+++ b/qemu-components/common/src/libqemu-cxx/target-info.cc
@@ -16,6 +16,9 @@ const char* get_target_name(Target t)
     case AARCH64:
         return "AArch64";
 
+    case ARM:
+        return "ARM (32-bit)";
+
     case RISCV64:
         return "RISC-V (64 bits)";
 
@@ -40,6 +43,10 @@ const char* get_target_name(Target t)
 #define LIBQEMU_TARGET_aarch64_LIBRARY nullptr
 #endif
 
+#ifndef LIBQEMU_TARGET_arm_LIBRARY
+#define LIBQEMU_TARGET_arm_LIBRARY nullptr
+#endif
+
 #ifndef LIBQEMU_TARGET_riscv64_LIBRARY
 #define LIBQEMU_TARGET_riscv64_LIBRARY nullptr
 #endif
@@ -66,6 +73,9 @@ const char* get_target_lib(Target t)
     case AARCH64:
         return LIBQEMU_TARGET_aarch64_LIBRARY;
 
+    case ARM:
+        return LIBQEMU_TARGET_arm_LIBRARY;
+
     case RISCV64:
         return LIBQEMU_TARGET_riscv64_LIBRARY;