Items to address from prototype 1.2 board fabrication

[mikenye]

Connectors

• u.fl connectors instead of / to compliment the SMA connectors
• RF_IN fouls on FPGA board Ethernet

Bias-Tee

• Implement bias-tee that can be turned on/off via FPGA pin

TADJ Trimpot

• Find optimum TADJ voltage & replace with simple resistor divider

Fiducials

• JLCPCB placed their own fiducials.
• We already had 3x fiducials on the board.
• Theirs were thru-hole, ours were plated.
• Perhaps we need to change the fiducial type so JLCPCB don't have to add any?

ADC VREF

• Measured (TP21) at 1.15V, this seems high - datasheet shows 1V +/- 30mV.

Others

• PPS LED way too bright
• TADJ bottoms out at cc 0.82V (expected 0.80V)

[shaneshort]

AD8138 interface likely too heavy for the ADL5513 output.

R37 is 499 Ω, and with the matched 499 Ω AD8138 feedback network the detector sees roughly a ~665 Ω effective single-ended load. The ADL5513 VOUT is a log/video output, not a low-impedance RF/baseband line driver. Its normal measurement load is basically VSET at high impedance, and the datasheet calls out limited output current drive. Lifting R37 proves the detector works when that load is removed.

For the prototype, we will try:

• Replace R37/R38/R39/R40 together with 4.99 kΩ or 10 kΩ.
• Keep all four values equal so the AD8138 gain/balance stays correct.
• Re-test TP13, TP16 +OUT, and TP17 -OUT.

That will change the detector load from roughly 665 Ω to about:

4.99k network -> ~6.7 kΩ effective input
10k network -> ~13.3 kΩ effective input

That should be much more reasonable for VOUT.

For the next PCB spin, maybe we consider a buffer between ADL5513 VOUT/VSET/TP13 and the AD8138 if we want to keep the AD8138 in its recommended low-value, high-speed 499 Ω network. We should use a unity-gain video/baseband op amp with high input impedance, 3.3 V single-supply operation, output swing covering roughly 0.5 V to 2.0 V, and enough bandwidth for the detector video bandwidth.

TLDR: the AD8138 network is valid for a low-impedance source, but the ADL5513 output should be treated as a high-impedance voltage signal. Either raise the AD8138 resistor network substantially or buffer it.

[mikenye]

We could likely tie the shutdown pins of the LNAs to FPGA pins.

This would allow one or both of the LNAs to be shutdown.

[shaneshort]

We could likely tie the shutdown pins of the LNAs to FPGA pins.

This would allow one or both of the LNAs to be shutdown.

I don't know if we need that, maybe a pad we can short? what's the utility?

[mikenye]

We could likely tie the shutdown pins of the LNAs to FPGA pins.

This would allow one or both of the LNAs to be shutdown.

I don't know if we need that, maybe a pad we can short? what's the utility?

Reduce gain. I'm wondering if our pulses look weak due to over driving the log detector...

[mikenye]

Random thought from our weekend debugging session...

The TA2003A has a temperature coefficient is listed as −36 ppm/K. At 1090 MHz, that is about 39 kHz per °C. Over a 60 °C change, the filter centre can move by about 2.35 MHz.

When we re-touch the board and the filters get hot - this might explain weak signals?

[mikenye]

Other things I'd like to try / experiment with:

Slope adjustment of ADL5513:

• Lift the ADL5513
• Cut trace between pin 12 (VOUT) and pin 11 (VSET)
• Bodge wire on pin 11 (VSET)
• Bodge wire on pin 14 (CPLF)
• Replace ADL5513
• Scratch off some solder mask near TP13
• Solder first 10kΩ resistor to TP13
• Solder second 10kΩ resistor to other end of first, with bodge wire to pin 11
• Solder other end of second resistor to GND where solder mask removed.
• Basically making a voltage divider for VOUT to VSET.

From this:

To this:

[mikenye]

Other things I'd like to try / experiment with:

Offset ADC at noise floor of ADL5513 output:

• Branch the VOUT of the ADL5513 (TP13).
• Through op-amp in unity gain as a buffer.
• Into a low-pass filter (kHz), so the output excludes the ADS-B pulses, but includes the noise floor.
• Cut trace from via to pin 1 of C73 (remove VREF voltage ADC).
• Output of low-pass filter into TP21.

By making the zero level of the ADC the noise floor voltage, we should increase our dynamic range and make the receiver more sensitive.

[mikenye]

Other things I'd like to try / experiment with:

Buffer output of ADL5513:

• Cut trace from ADL5513 into pin 2 of R37 (disconnect VOUT from ADL5513 from gain/feedback network of AD8138 ADC driver)
• Hook up op-amp as unity gain buffer as-per schematic below

We should be able to keep the 499Ω gain/feedback resistors on the AD8138 - this might perform better than no-buffer and changing the gain/feedback resistors to higher values (which will slow down the AD8138).

When doing this, we could also attempt to bypass the AD8138 and drive the ADC directly, through a balun as-per figure 29 in the AD9203 data sheet (although, if we do this, we remove the potential benefits of offsetting the noise as-per my previous comment).

[mikenye]

Other things I'd like to try / experiment with:

Offset ADC at noise floor of ADL5513 output:

• Branch the VOUT of the ADL5513 (TP13).
• Through op-amp in unity gain as a buffer.
• Into a low-pass filter (kHz), so the output excludes the ADS-B pulses, but includes the noise floor.
• Cut trace from via to pin 1 of C73 (remove VREF voltage ADC).
• Output of low-pass filter into TP21.

By making the zero level of the ADC the noise floor voltage, we should increase our dynamic range and make the receiver more sensitive.

I simulated this in Falstad Circuit Simulator:

It lifts the ADC offset (red line) to the noise floor (bottom of the ADSB pulses). I think this is definitely worth pursuing.

Sim code:

$ 1 1e-8 69.34413510434165 49 5 50
x 32 -58 606 -55 4 18 Simulated\sADL5513\soutput\swith\sgated\sADS-B\sburst\sand\sslow\sADC\soffset
x 32 -30 433 -27 4 14 Gate\sis\s200Hz\spulse,\s2.4\spercent\sduty,\sso\s120us\sburst\severy\s5ms
x 31 -7 454 -4 4 14 Pulse\srail\sis\s1MHz\ssquare\sfrom\s0.45V\sto\s0.90V;\sbaseline\srail\sis\s0.45V
R 96 112 64 112 0 2 1000000 0.225 0.675 0 0.5
R 96 208 64 208 0 0 40 0.45 0 0 0.5
R -32 160 -96 160 4 5 200 5 0 0 0.15915494309189535
w 96 112 192 112 0
w 96 208 192 208 0
159 192 112 352 112 0 20 10000000000
159 192 208 352 208 1 20 10000000000
w 352 160 384 160 0
r 384 160 480 160 0 100
c 480 160 480 240 0 1.6e-10 0.8994857510437563
g 480 240 480 256 0
O 480 160 496 128 1 0
x 458 111 628 114 4 14 Simulated\sADL5513\sOutput
r 480 160 640 160 0 100000
c 640 160 640 240 0 0.000001 0.4709459449499921
g 640 240 640 256 0
O 640 160 736 160 1 0
x 699 145 769 148 4 14 ADC\sOffset
x 317 293 632 296 4 14 100\sohm\s160pF\sapprox\s10MHz\sdetector\sbandwidth
x 653 294 923 297 4 14 100k\s1uF\sslow\sbaseline\sfollower,\stau\s100ms
w 352 160 352 112 0
w 352 160 352 208 0
w 272 128 272 160 0
w 272 160 -32 160 0
w -32 160 -32 224 0
w -32 224 272 224 0
o 14 8 0 4098 1.25 0.1 0 2 19 0

[mikenye]

AD8138 interface likely too heavy for the ADL5513 output.

R37 is 499 Ω, and with the matched 499 Ω AD8138 feedback network the detector sees roughly a ~665 Ω effective single-ended load. The ADL5513 VOUT is a log/video output, not a low-impedance RF/baseband line driver. Its normal measurement load is basically VSET at high impedance, and the datasheet calls out limited output current drive. Lifting R37 proves the detector works when that load is removed.

For the prototype, we will try:

• Replace R37/R38/R39/R40 together with 4.99 kΩ or 10 kΩ.
• Keep all four values equal so the AD8138 gain/balance stays correct.
• Re-test TP13, TP16 +OUT, and TP17 -OUT.

That will change the detector load from roughly 665 Ω to about:

4.99k network -> ~6.7 kΩ effective input 10k network -> ~13.3 kΩ effective input

That should be much more reasonable for VOUT.

For the next PCB spin, maybe we consider a buffer between ADL5513 VOUT/VSET/TP13 and the AD8138 if we want to keep the AD8138 in its recommended low-value, high-speed 499 Ω network. We should use a unity-gain video/baseband op amp with high input impedance, 3.3 V single-supply operation, output swing covering roughly 0.5 V to 2.0 V, and enough bandwidth for the detector video bandwidth.

TLDR: the AD8138 network is valid for a low-impedance source, but the ADL5513 output should be treated as a high-impedance voltage signal. Either raise the AD8138 resistor network substantially or buffer it.

Addressed in 4c48fe0