Hi there, I am working on porting RISC-V processor with clic interrupt system, not the clint + plic version.
For clic spec, please check https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc
I tried to use a lowest priority interrupt(Machine software interrupt) to do context switch, but I found that if I trigger this interrupt in task context, it will not be handled due to interrupt is disabled globally, but if I enable irq, the kernel will work incorrectly, could you give me some hints on it?
You can find my porting code in https://github.com/nuclei-community/lk/tree/dev_nuclei/arch/riscv
Thanks
Huaqi