diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index f9c2d91d..b0323c13 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -14,6 +14,8 @@ repos: rev: v2.4.2 hooks: - id: codespell + additional_dependencies: + - tomli - repo: https://github.com/espressif/check-copyright/ rev: v1.1.2 @@ -49,4 +51,4 @@ repos: hooks: - id: clang-format files: \.(c|h|cpp|hpp|cc|cxx)$ - exclude: ^(include/esp-stub-lib/miniz\.h|src/target/esp8266/src/miniz\.c|src/target/.*/include/soc/.*\.h)$ + exclude: ^(include/esp-stub-lib/miniz\.h|src/target/esp8266/src/miniz\.c|src/target/.*/include/(soc/.*\.h|esp_rom_caps\.h))$ diff --git a/pyproject.toml b/pyproject.toml index 3e7cbf66..40c964c2 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -18,3 +18,4 @@ [tool.codespell] write-changes = false + skip = "src/target/*/include/soc/*.h,src/target/*/include/esp_rom_caps.h,src/target/*/ld/*.rom.*.ld" diff --git a/src/target/esp32c5/include/esp_rom_caps.h b/src/target/esp32c5/include/esp_rom_caps.h index d4fb7089..1ae240bc 100644 --- a/src/target/esp32c5/include/esp_rom_caps.h +++ b/src/target/esp32c5/include/esp_rom_caps.h @@ -4,38 +4,39 @@ * SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * THIS FILE WAS AUTOMATICALLY GENERATED BY esptool-autogen. + * Source: /home/dragon/Projects/gitlab_esptool/esp-flasher-stub/esp-stub-lib/esp-rom/rom/target/esp32c5/interface-esp32c5.yml (md5: 6657bed8cbdb120b8c8846ca5859a556) + * DO NOT EDIT. + */ + #pragma once -#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian -#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian -#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library -#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM -#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. +#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian +#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian +#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library +#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM +#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. #define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking -#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` -#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib -#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver -#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver -#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library -#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() -#define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() -#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table -#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver -#define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver -#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs TODO: IDF-10110 need refactor -#define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included -#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT \ - (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions) +#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib +#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver +#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver +#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library +#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() +#define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver +#define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver +#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs +#define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included +#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock -#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE \ - (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap -#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init -#define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information -#define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB \ - (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. -#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. -#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) -#define ESP_ROM_CLIC_INT_THRESH_PATCH \ - (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF -#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY \ - (1) // ROM mem/str functions are not optimized well for misaligned memory access. +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size for flash mmap +#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM does not init cache MMU for RAM APP +#define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information +#define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports HP core jump to RTC memory after deepsleep wakeup +#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM +#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) +#define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F +#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized for misaligned memory access diff --git a/src/target/esp32c5/include/soc/reg_base.h b/src/target/esp32c5/include/soc/reg_base.h index a68fcfb4..0eef9ee8 100644 --- a/src/target/esp32c5/include/soc/reg_base.h +++ b/src/target/esp32c5/include/soc/reg_base.h @@ -4,110 +4,76 @@ * SPDX-License-Identifier: Apache-2.0 OR MIT */ -#pragma once - -/** - * @brief Peripheral 0 Modules - * - */ -#define DR_REG_UART0_BASE 0x60000000 -#define DR_REG_UART1_BASE 0x60001000 -#define DR_REG_SPIMEM0_BASE 0x60002000 -#define DR_REG_SPIMEM1_BASE 0x60003000 -#define DR_REG_I2C_BASE 0x60004000 -#define DR_REG_UHCI_BASE 0x60005000 -#define DR_REG_RMT_BASE 0x60006000 -#define DR_REG_LEDC_BASE 0x60007000 -#define DR_REG_TIMERG0_BASE 0x60008000 -#define DR_REG_TIMERG1_BASE 0x60009000 -#define DR_REG_SYSTIMER_BASE 0x6000A000 -#define DR_REG_TWAI0_BASE 0x6000B000 -#define DR_REG_I2S_BASE 0x6000C000 -#define DR_REG_TWAI1_BASE 0x6000D000 -#define DR_REG_APB_SARADC_BASE 0x6000E000 -#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 -#define DR_REG_INTMTX_BASE 0x60010000 -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE -#define DR_REG_PCNT_BASE 0x60012000 -#define DR_REG_SOC_ETM_BASE 0x60013000 -#define DR_REG_MCPWM_BASE 0x60014000 -#define DR_REG_PARL_IO_BASE 0x60015000 -#define DR_REG_PVT_MONITOR_BASE 0x60019000 -#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 - -/** - * @brief Peripheral 1 Modules - * - */ -#define DR_REG_AHB_DMA_BASE 0x60080000 -#define DR_REG_SPI2_BASE 0x60081000 -#define DR_REG_BITSCRAMBLER_BASE 0x60082000 -#define DR_REG_KEYMNG_BASE 0x60087000 -#define DR_REG_AES_BASE 0x60088000 -#define DR_REG_SHA_BASE 0x60089000 -#define DR_REG_RSA_BASE 0x6008A000 -#define DR_REG_ECC_MULT_BASE 0x6008B000 -#define DR_REG_DS_BASE 0x6008C000 -#define DR_REG_HMAC_BASE 0x6008D000 -#define DR_REG_ECDSA_BASE 0x6008E000 - -/** - * @brief HP Top Peripheral Modules - * - */ -#define DR_REG_IO_MUX_BASE 0x60090000 -#define DR_REG_GPIO_BASE 0x60091000 -#define DR_REG_GPIO_EXT_BASE 0x60091e00 -#define DR_REG_MEM_MONITOR_BASE 0x60092000 -#define DR_REG_PAU_BASE 0x60093000 -#define DR_REG_HP_SYSTEM_BASE 0x60095000 -#define DR_REG_PCR_BASE 0x60096000 -#define DR_REG_TEE_BASE 0x60098000 -#define DR_REG_HP_APM_BASE 0x60099000 -#define DR_REG_LP_APM0_BASE 0x60099800 -#define DR_REG_MISC_BASE 0x6009F000 - -/** - * @brief Modem Module - * +/* + * THIS FILE WAS AUTOMATICALLY GENERATED BY esptool-autogen. + * Source: /home/dragon/Projects/gitlab_esptool/esp-flasher-stub/esp-stub-lib/esp-rom/rom/target/esp32c5/interface-esp32c5.yml (md5: 6657bed8cbdb120b8c8846ca5859a556) + * DO NOT EDIT. */ -#define DR_REG_MODEM0_BASE 0x600A0000 -#define DR_REG_MODEM1_BASE 0x600AC000 -#define DR_REG_MODEM_PWR0_BASE 0x600AD000 -#define DR_REG_MODEM_PWR1_BASE 0x600AF000 -#define PWDET_CONF_REG 0x600A0810 -#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 -#define IEEE802154_REG_BASE 0x600A3000 - -/** - * @brief LP System (RTC) Modules - * - */ -#define DR_REG_PMU_BASE 0x600B0000 -#define DR_REG_LP_CLKRST_BASE 0x600B0400 -#define DR_REG_LP_TIMER_BASE 0x600B0C00 -#define DR_REG_LP_AON_BASE 0x600B1000 -#define DR_REG_LP_UART_BASE 0x600B1400 -#define DR_REG_LP_I2C_BASE 0x600B1800 -#define DR_REG_LP_WDT_BASE 0x600B1C00 -#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400 -#define DR_REG_LPPERI_BASE 0x600B2800 -#define DR_REG_LP_ANA_BASE 0x600B2C00 -#define DR_REG_HUK_BASE 0x600B3000 -#define DR_REG_LP_TEE_BASE 0x600B3400 -#define DR_REG_LP_APM_BASE 0x600B3800 -#define DR_REG_LP_IO_MUX_BASE 0x600B4000 -#define DR_REG_LP_GPIO_BASE 0x600B4400 -#define DR_REG_EFUSE_BASE 0x600B4800 -#define DR_REG_OTP_DEBUG_BASE 0x600B4D00 +#pragma once -/** - * @brief CPU Peripheral Modules - * - */ -#define DR_REG_TRACE_BASE 0x600C0000 -#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 -#define DR_REG_INTPRI_BASE 0x600C5000 -#define DR_REG_CACHE_BASE 0x600C8000 // CACHE_CONFIG/EXTMEM -#define DR_REG_CLINT_M_BASE 0x20000000 +#define DR_REG_UART0_BASE 0x60000000 +#define DR_REG_UART1_BASE 0x60001000 +#define DR_REG_SPIMEM0_BASE 0x60002000 +#define DR_REG_SPIMEM1_BASE 0x60003000 +#define DR_REG_I2C_BASE 0x60004000 +#define DR_REG_UHCI_BASE 0x60005000 +#define DR_REG_RMT_BASE 0x60006000 +#define DR_REG_LEDC_BASE 0x60007000 +#define DR_REG_TIMERG0_BASE 0x60008000 +#define DR_REG_TIMERG1_BASE 0x60009000 +#define DR_REG_SYSTIMER_BASE 0x6000A000 +#define DR_REG_TWAI0_BASE 0x6000B000 +#define DR_REG_I2S_BASE 0x6000C000 +#define DR_REG_TWAI1_BASE 0x6000D000 +#define DR_REG_APB_SARADC_BASE 0x6000E000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 +#define DR_REG_INTMTX_BASE 0x60010000 +#define DR_REG_PCNT_BASE 0x60012000 +#define DR_REG_SOC_ETM_BASE 0x60013000 +#define DR_REG_MCPWM_BASE 0x60014000 +#define DR_REG_PARL_IO_BASE 0x60015000 +#define DR_REG_PVT_MONITOR_BASE 0x60019000 +#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 +#define DR_REG_AHB_DMA_BASE 0x60080000 +#define DR_REG_SPI2_BASE 0x60081000 +#define DR_REG_BITSCRAMBLER_BASE 0x60082000 +#define DR_REG_KEYMNG_BASE 0x60087000 +#define DR_REG_AES_BASE 0x60088000 +#define DR_REG_SHA_BASE 0x60089000 +#define DR_REG_RSA_BASE 0x6008A000 +#define DR_REG_ECC_MULT_BASE 0x6008B000 +#define DR_REG_DS_BASE 0x6008C000 +#define DR_REG_HMAC_BASE 0x6008D000 +#define DR_REG_ECDSA_BASE 0x6008E000 +#define DR_REG_IO_MUX_BASE 0x60090000 +#define DR_REG_GPIO_BASE 0x60091000 +#define DR_REG_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_PAU_BASE 0x60093000 +#define DR_REG_HP_SYSTEM_BASE 0x60095000 +#define DR_REG_PCR_BASE 0x60096000 +#define DR_REG_TEE_BASE 0x60098000 +#define DR_REG_HP_APM_BASE 0x60099000 +#define DR_REG_MISC_BASE 0x6009F000 +#define DR_REG_PMU_BASE 0x600B0000 +#define DR_REG_LP_CLKRST_BASE 0x600B0400 +#define DR_REG_LP_TIMER_BASE 0x600B0C00 +#define DR_REG_LP_AON_BASE 0x600B1000 +#define DR_REG_LP_UART_BASE 0x600B1400 +#define DR_REG_LP_I2C_BASE 0x600B1800 +#define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400 +#define DR_REG_LPPERI_BASE 0x600B2800 +#define DR_REG_LP_ANA_BASE 0x600B2C00 +#define DR_REG_HUK_BASE 0x600B3000 +#define DR_REG_LP_TEE_BASE 0x600B3400 +#define DR_REG_LP_APM_BASE 0x600B3800 +#define DR_REG_LP_IO_MUX_BASE 0x600B4000 +#define DR_REG_LP_GPIO_BASE 0x600B4400 +#define DR_REG_EFUSE_BASE 0x600B4800 +#define DR_REG_OTP_DEBUG_BASE 0x600B4D00 +#define DR_REG_TRACE_BASE 0x600C0000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 +#define DR_REG_INTPRI_BASE 0x600C5000 +#define DR_REG_CACHE_BASE 0x600C8000 +#define DR_REG_CLINT_M_BASE 0x20000000 diff --git a/src/target/esp32c5/include/soc/soc.h b/src/target/esp32c5/include/soc/soc.h index b671cce4..0f343183 100644 --- a/src/target/esp32c5/include/soc/soc.h +++ b/src/target/esp32c5/include/soc/soc.h @@ -4,64 +4,62 @@ * SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * THIS FILE WAS AUTOMATICALLY GENERATED BY esptool-autogen. + * Source: /home/dragon/Projects/gitlab_esptool/esp-flasher-stub/esp-stub-lib/esp-rom/rom/target/esp32c5/interface-esp32c5.yml (md5: 6657bed8cbdb120b8c8846ca5859a556) + * DO NOT EDIT. + */ + #pragma once /* Overall memory map */ -#define SOC_IROM_LOW 0x42000000 -#define SOC_IROM_HIGH 0x44000000 -#define SOC_EXTRAM_DATA_LOW 0x42000000 +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH 0x44000000 +#define SOC_EXTRAM_DATA_LOW 0x42000000 #define SOC_EXTRAM_DATA_HIGH 0x44000000 -#define SOC_DROM_LOW SOC_IROM_LOW -#define SOC_DROM_HIGH SOC_IROM_HIGH -#define SOC_IROM_MASK_LOW 0x40000000 -#define SOC_IROM_MASK_HIGH 0x40050000 -#define SOC_DROM_MASK_LOW 0x40000000 -#define SOC_DROM_MASK_HIGH 0x40050000 -#define SOC_IRAM_LOW 0x40800000 -#define SOC_IRAM_HIGH 0x40860000 -#define SOC_DRAM_LOW 0x40800000 -#define SOC_DRAM_HIGH 0x40860000 -#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C5 only has 16k LP memory -#define SOC_RTC_IRAM_HIGH 0x50004000 -#define SOC_RTC_DRAM_LOW 0x50000000 -#define SOC_RTC_DRAM_HIGH 0x50004000 -#define SOC_RTC_DATA_LOW 0x50000000 -#define SOC_RTC_DATA_HIGH 0x50004000 +#define SOC_DROM_LOW SOC_IROM_LOW +#define SOC_DROM_HIGH SOC_IROM_HIGH +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40050000 +#define SOC_DROM_MASK_LOW 0x40000000 +#define SOC_DROM_MASK_HIGH 0x40050000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40860000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40860000 +#define SOC_RTC_IRAM_LOW 0x50000000 +#define SOC_RTC_IRAM_HIGH 0x50004000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50004000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50004000 -//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. -#define SOC_DIRAM_IRAM_LOW 0x40800000 +#define SOC_DIRAM_IRAM_LOW 0x40800000 #define SOC_DIRAM_IRAM_HIGH 0x40860000 -#define SOC_DIRAM_DRAM_LOW 0x40800000 +#define SOC_DIRAM_DRAM_LOW 0x40800000 #define SOC_DIRAM_DRAM_HIGH 0x40860000 #define MAP_DRAM_TO_IRAM(addr) (addr) #define MAP_IRAM_TO_DRAM(addr) (addr) -// Region of memory accessible via DMA. See esp_ptr_dma_capable(). -#define SOC_DMA_LOW 0x40800000 +#define SOC_DMA_LOW 0x40800000 #define SOC_DMA_HIGH 0x40860000 -// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). -#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 +#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 #define SOC_BYTE_ACCESSIBLE_HIGH 0x40860000 -//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs -//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). -#define SOC_MEM_INTERNAL_LOW 0x40800000 -#define SOC_MEM_INTERNAL_HIGH 0x40860000 -#define SOC_MEM_INTERNAL_LOW1 0x40800000 -#define SOC_MEM_INTERNAL_HIGH1 0x40860000 +#define SOC_MEM_INTERNAL_LOW 0x40800000 +#define SOC_MEM_INTERNAL_HIGH 0x40860000 +#define SOC_MEM_INTERNAL_LOW1 0x40800000 +#define SOC_MEM_INTERNAL_HIGH1 0x40860000 -#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IROM_HIGH - SOC_IROM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IROM_HIGH - SOC_IROM_LOW) -// Region of address space that holds peripherals -#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_LOW 0x60000000 #define SOC_PERIPHERAL_HIGH 0x60100000 -// CPU sub-system region, contains interrupt config registers -#define SOC_CPU_SUBSYSTEM_LOW 0x20000000 +#define SOC_CPU_SUBSYSTEM_LOW 0x20000000 #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 -// Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x4085e5a0 -#define SOC_ROM_STACK_SIZE 0x2000 +#define SOC_ROM_STACK_SIZE 0x00002000 diff --git a/src/target/esp32c5/include/soc/soc_caps.h b/src/target/esp32c5/include/soc/soc_caps.h index d0152dd0..82a63f09 100644 --- a/src/target/esp32c5/include/soc/soc_caps.h +++ b/src/target/esp32c5/include/soc/soc_caps.h @@ -4,11 +4,15 @@ * SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * THIS FILE WAS AUTOMATICALLY GENERATED BY esptool-autogen. + * Source: /home/dragon/Projects/gitlab_esptool/esp-flasher-stub/esp-stub-lib/esp-rom/rom/target/esp32c5/interface-esp32c5.yml (md5: 6657bed8cbdb120b8c8846ca5859a556) + * DO NOT EDIT. + */ + #pragma once /*-------------------------- COMMON CAPS ---------------------------------------*/ -#define SOC_UART_HP_NUM (2) /*!< HP UART number */ - -// Memory Caps -#define SOC_RTC_FAST_MEM_SUPPORTED 1 -#define SOC_RTC_MEM_SUPPORTED 1 +#define SOC_UART_HP_NUM (2) +#define SOC_RTC_FAST_MEM_SUPPORTED (1) +#define SOC_RTC_MEM_SUPPORTED (1) diff --git a/src/target/esp32c5/ld/esp32c5.rom.extra.ld b/src/target/esp32c5/ld/esp32c5.rom.extra.ld index f1cd5372..7250a1d8 100644 --- a/src/target/esp32c5/ld/esp32c5.rom.extra.ld +++ b/src/target/esp32c5/ld/esp32c5.rom.extra.ld @@ -1,8 +1,14 @@ -/*************************************** - * Manually added ROM symbols for esp32c5 - * These symbols are not in the auto-generated ROM linker scripts - * but are needed for ECO version handling - ***************************************/ +/* + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +/* + * THIS FILE WAS AUTOMATICALLY GENERATED BY esptool-autogen. + * Source: /home/dragon/Projects/gitlab_esptool/esp-flasher-stub/esp-stub-lib/esp-rom/rom/target/esp32c5/interface-esp32c5.yml (md5: 6657bed8cbdb120b8c8846ca5859a556) + * DO NOT EDIT. + */ /* ROM version variables */ _rom_eco_version = 0x40000014;