docs(mappers): MMC1's module docs state the v2.8.2 write-filter rule

Copilot on #558: the `//!` preamble still said the port inhibits "a second
write on the CPU cycle immediately following an accepted write" and drops
"writes that fall on the cycle right after another accepted write". Both
halves went stale in dae2053, which made an ignored write count as the
last write too and made the bit-7 reset immune to the filter; the field
comment and the match arm were updated then, the crate docs were not.

The preamble now states the rule as implemented and as nesdev words it:
only the data bit of a write on the cycle after any serial-port write is
ignored, the reset is never ignored, and the read-modify-write instruction
is the case both games depend on (Bill & Ted on the dropped data write,
Shinsenden on the reset landing). It names the correction and its audit
row so a reader of the older behaviour knows why it changed.

Comment-only. cargo test -p rustynes-mappers m001 (23 passed), rustdoc
-D warnings on the crate and fmt are clean.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014qfTKi2M3swo7qnwvYCkDj

Author: doublegate

crates/rustynes-mappers/src/m001_mmc1.rs

@@ -11,11 +11,17 @@
 //! has bit 7 set resets the shift register and ORs the control register
 //! with `$0C` (forcing PRG mode 3 = "fix last bank @ $C000").
 //!
-//! Consecutive-write bug: real hardware inhibits the register from accepting
-//! a second write on the CPU cycle immediately following an accepted write.
-//! Bill & Ted's Excellent Adventure relies on this. We track the cycle
-//! counter via [`Mapper::notify_cpu_cycle`] and drop writes that fall on the
-//! cycle right after another accepted write.
+//! Consecutive-write bug: on real hardware the serial port ignores the DATA
+//! bit of a write that lands on the CPU cycle immediately after another
+//! serial-port write, whether that earlier write was accepted or itself
+//! ignored (nesdev: it "ignores every write after the first"). A write with
+//! bit 7 set is never ignored: the reset takes effect on any cycle. A
+//! read-modify-write instruction's two back-to-back writes are the case that
+//! matters: Bill & Ted's Excellent Adventure relies on the second data write
+//! being dropped, and Shinsenden on a reset in that second write landing. We
+//! track the cycle counter via [`Mapper::notify_cpu_cycle`]. Until v2.8.2 the
+//! reset was filtered too (RTL audit R-3.5a, which found the `MiSTer` core right
+//! and this implementation wrong).
 //!
 //! The default revision when the cartridge header lacks an NES 2.0 submapper
 //! byte is **Sharp** (project policy: Star Trek: 25th Anniversary requires