diff --git a/.github/workflows/creator.yml b/.github/workflows/creator.yml index 55091bfbf..200a3ad02 100644 --- a/.github/workflows/creator.yml +++ b/.github/workflows/creator.yml @@ -110,7 +110,6 @@ jobs: name: Build CLI (${{ matrix.os }}) runs-on: ubuntu-latest needs: build-cli-wasm - if: github.event_name != 'pull_request' strategy: matrix: include: @@ -198,6 +197,7 @@ jobs: name: Publish nightly release runs-on: ubuntu-latest needs: [build-cli-binaries, package-architectures, test] + if: github.event_name != 'pull_request' concurrency: group: nightly-release cancel-in-progress: false @@ -229,7 +229,7 @@ jobs: name: Publish latest tagged release runs-on: ubuntu-latest needs: [build-cli-binaries, package-architectures, test] - if: github.ref_type == 'tag' + if: github.ref_type == 'tag' && github.event_name != 'pull_request' concurrency: group: stable-release cancel-in-progress: false diff --git a/README.md b/README.md index 96d8882bc..2106a0bef 100644 --- a/README.md +++ b/README.md @@ -116,6 +116,30 @@

Publications

+### 2026 + +
+:newspaper: CREATOR-Sail: A RISC-V web simulator based on Sail ISA specification + + * Journal paper: Journal of Systems Architecture + * Authors: Juan Carlos Cano-Resa, Félix García-Carballeira, Diego Camarmas-Alonso, Alejandro Calderón-Mateos + * [:link: Open publication](https://doi.org/10.1016/j.sysarc.2026.103809) + ```bibtex + @article{CANORESA2026103809, + title = {CREATOR-Sail: A RISC-V web simulator based on Sail ISA specification}, + journal = {Journal of Systems Architecture}, + volume = {176}, + pages = {103809}, + year = {2026}, + issn = {1383-7621}, + doi = {https://doi.org/10.1016/j.sysarc.2026.103809}, + url = {https://www.sciencedirect.com/science/article/pii/S138376212600127X}, + author = {Juan Carlos Cano-Resa and Felix Garcia-Carballeira and Diego Camarmas-Alonso and Alejandro Calderon-Mateos}, + keywords = {RISC-V, Sail, Web simulator, Extensible simulator, Instruction set architecture}, + } + ``` +
+ ### 2025
@@ -232,6 +256,7 @@ * [:link: Open publication](https://doi.org/10.5281/zenodo.8378899) ```bibtex @proceedings{diego_camarmas_alonso_2023_8378899, + author = {Diego Camarmas-Alonso and Felix Garcia-Carballeira and Alejandro Calderon-Mateos and Elías Del-Pozo-Puñal}, title = {{Integración del simulador CREATOR con hardware RISC-V: caso de estudio con microcontrolador ESP32}}, year = 2023, publisher = {Zenodo}, @@ -280,6 +305,7 @@ * [:link: Open publication](http://doi.org/10.5281/zenodo.5130302) ```bibtex @proceedings{diego_camarmas_alonso_2021_5130302, + author = {Diego Camarmas-Alonso and Felix Garcia-Carballeira and Alejandro Calderon-Mateos and Elías Del-Pozo-Puñal}, title = {{CREATOR: Simulador didáctico y genérico para la programación en ensamblador}}, year = 2021, publisher = {Zenodo}, diff --git a/architecture/6502.yml b/architecture/6502.yml index d5e4dd99a..0d5fcbbcf 100644 --- a/architecture/6502.yml +++ b/architecture/6502.yml @@ -14,11 +14,11 @@ config: start_address: 0x0 pc_offset: 0 -components: +register_files: - name: Control registers - type: ctrl_registers + type: ctrl double_precision: false - elements: + registers: - name: - PC nbits: 8 @@ -30,9 +30,9 @@ components: - write - program_counter - name: Integer registers - type: int_registers + type: int double_precision: false - elements: + registers: - name: - A encoding: 0 diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index 7c01aae82..1fd69738d 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -19,11 +19,11 @@ config: - name: CreatorAssembler description: "Default CREATOR assembler" -components: +register_files: - name: Control registers - type: ctrl_registers + type: ctrl double_precision: false - elements: + registers: - name: - PC nbits: 32 @@ -128,9 +128,9 @@ components: - read - write - name: Integer registers - type: int_registers + type: int double_precision: false - elements: + registers: - name: - "0" - zero @@ -462,9 +462,9 @@ components: - read - write - name: 32-bit FP registers - type: fp_registers + type: float double_precision: false - elements: + registers: - name: - f0 - FP0 diff --git a/architecture/RISCV/RV32IMFD.yml b/architecture/RISCV/RV32IMFD.yml index 825c89625..86d8ac376 100644 --- a/architecture/RISCV/RV32IMFD.yml +++ b/architecture/RISCV/RV32IMFD.yml @@ -49,11 +49,11 @@ extensions: description: "RV32/RV64 Privileged instructions" type: extension -components: +register_files: - name: Control registers - type: ctrl_registers + type: ctrl double_precision: false - elements: + registers: - name: - pc nbits: 32 @@ -149,9 +149,9 @@ components: - write - name: Integer registers - type: int_registers + type: int double_precision: false - elements: + registers: - name: - x0 - zero @@ -490,9 +490,9 @@ components: - write - name: Floating point registers - type: fp_registers + type: float double_precision: true - elements: + registers: - name: - f0 - ft0 @@ -2075,25 +2075,6 @@ instructions: debugging environment. It generates a breakpoint exception and performs no other operation. - # TODO: delete this when devices exist - - name: print_int - type: Syscall - template: Custom - fields: - - field: opcode - value: "1110011" - - field: funct12 - type: cop - startbit: 31 - stopbit: 20 - value: "000000000010" - - field: zeros - type: cop - startbit: 19 - stopbit: 7 - value: "0000000000000" - definition: "CAPI.SYSCALL.print(registers.a0, 'int32');" - M: # ____ __ __ _____ ____ __ __ # | _ \\ \ / /|___ /|___ \ | \/ | @@ -2213,7 +2194,9 @@ instructions: - field: funct3 value: "110" definition: | - registers[rd] = registers[rs1] % registers[rs2]; + registers[rd] = CAPI.FP.int2uint( + CAPI.FP.uint2int(registers[rs1]) % CAPI.FP.uint2int(registers[rs2]) + ); help: Perform an XLEN-bit by XLEN-bit signed integer reminder of rs1 by rs2. diff --git a/architecture/RISCV/RV64IMFD.yml b/architecture/RISCV/RV64IMFD.yml index 5efea7a0a..eeb5b5f7e 100644 --- a/architecture/RISCV/RV64IMFD.yml +++ b/architecture/RISCV/RV64IMFD.yml @@ -50,11 +50,11 @@ extensions: description: "RV32/RV64 Privileged instructions" type: extension -components: +register_files: - name: Control registers - type: ctrl_registers + type: ctrl double_precision: false - elements: + registers: - name: - pc nbits: 64 @@ -150,9 +150,9 @@ components: - write - name: Integer registers - type: int_registers + type: int double_precision: false - elements: + registers: - name: - x0 - zero @@ -491,9 +491,9 @@ components: - write - name: Floating point registers - type: fp_registers + type: float double_precision: true - elements: + registers: - name: - f0 - ft0 @@ -2412,7 +2412,9 @@ instructions: - field: funct3 value: "110" definition: | - registers[rd] = registers[rs1] % registers[rs2]; + registers[rd] = CAPI.FP.int2uint( + CAPI.FP.uint2int(registers[rs1]) % CAPI.FP.uint2int(registers[rs2]) + ); help: Perform an XLEN-bit by XLEN-bit signed integer reminder of rs1 by rs2. @@ -2447,7 +2449,7 @@ instructions: - field: funct3 value: "010" - field: rd - type: SFP-Reg + type: DFP-Reg definition: | let addr = registers[rs1] + imm; if (CAPI.VALIDATION.isMisaligned(addr, 4)) @@ -3076,7 +3078,7 @@ instructions: - field: funct3 value: "010" - field: rs2 - type: SFP-Reg + type: DFP-Reg definition: | let value = registers[rs2] & 0xFFFFFFFFn; let addr = registers[rs1] + imm; @@ -3107,7 +3109,7 @@ instructions: let addr = registers[rs1] + imm; if (CAPI.VALIDATION.isMisaligned(addr, 8)) CAPI.VALIDATION.raise('The memory must be aligned'); - registers[rd] = CAPI.MEM.read(8, 8, rd, false); + registers[rd] = CAPI.MEM.read(addr, 8, rd, false); help: Load a double-precision floating-point value from memory into floating-point register rd. - name: fadd.d @@ -3182,7 +3184,7 @@ instructions: - field: rd type: DFP-Reg - field: rs1 - type: SFP-Reg + type: DFP-Reg - field: funct7 value: "0100001" - field: funct5 @@ -3280,7 +3282,7 @@ instructions: optional: true order: 3 - field: rd - type: SFP-Reg + type: DFP-Reg - field: rs1 type: DFP-Reg preoperation: | @@ -4138,30 +4140,30 @@ pseudoinstructions: - name: fabs.s fields: - field: rs1 - type: SFP-Reg + type: DFP-Reg suffix: "," - field: rs2 - type: SFP-Reg + type: DFP-Reg definition: | fsgnjx.s rs1, rs2, rs2; - name: fmv.s fields: - field: rs1 - type: SFP-Reg + type: DFP-Reg suffix: "," - field: rs2 - type: SFP-Reg + type: DFP-Reg definition: | fsgnj.s rs1, rs2, rs2; - name: fneg.s fields: - field: rs1 - type: SFP-Reg + type: DFP-Reg suffix: "," - field: rs2 - type: SFP-Reg + type: DFP-Reg definition: | fsgnjn.s rs1, rs2, rs2; D: diff --git a/architecture/RISCV/SRV32.yml b/architecture/RISCV/SRV32.yml index 1bc57cd10..cb48e05e8 100644 --- a/architecture/RISCV/SRV32.yml +++ b/architecture/RISCV/SRV32.yml @@ -44,11 +44,11 @@ extensions: Zicsr: description: RV32/RV64 Zicsr Standard Extension type: extension -components: +register_files: - name: Control registers - type: ctrl_registers + type: ctrl double_precision: false - elements: + registers: - name: - PC nbits: 32 @@ -60,9 +60,9 @@ components: - write - program_counter - name: Integer registers - type: int_registers + type: int double_precision: false - elements: + registers: - name: - x0 - zero @@ -400,9 +400,9 @@ components: - read - write - name: Floating point registers - type: fp_registers + type: float double_precision: true - elements: + registers: - name: - f0 - ft0 @@ -738,7 +738,7 @@ components: - name: Vectorial registers type: v_registers double_precision: true - elements: + registers: - name: - v0 - vt0 @@ -1062,8 +1062,8 @@ components: - name: Control state registers type: csr_registers double_precision: false - elements: -# USER registers + registers: + # USER registers - name: - ustatus nbits: 32 @@ -1136,7 +1136,7 @@ components: properties: - read - write -# SUPERVISOR registers + # SUPERVISOR registers - name: - sstatus nbits: 32 @@ -1236,7 +1236,7 @@ components: properties: - read - write -# MACHINE REGISTERS + # MACHINE REGISTERS - name: - mstatus nbits: 32 @@ -1354,7 +1354,7 @@ components: properties: - read - write -# COMMON REGISTERS + # COMMON REGISTERS - name: - cycle nbits: 32 @@ -2771,7 +2771,9 @@ instructions: - field: funct3 value: "110" definition: | - registers[rd] = registers[rs1] % registers[rs2]; + registers[rd] = CAPI.FP.int2uint( + CAPI.FP.uint2int(registers[rs1]) % CAPI.FP.uint2int(registers[rs2]) + ); help: Perform an XLEN-bit by XLEN-bit signed integer reminder of rs1 by rs2. - name: remu diff --git a/architecture/RISCV/SRV64.yml b/architecture/RISCV/SRV64.yml index ff392e157..16d4ad471 100644 --- a/architecture/RISCV/SRV64.yml +++ b/architecture/RISCV/SRV64.yml @@ -44,11 +44,11 @@ extensions: Zicsr: description: RV32/RV64 Zicsr Standard Extension type: extension -components: +register_files: - name: Control registers - type: ctrl_registers + type: ctrl double_precision: false - elements: + registers: - name: - PC nbits: 64 @@ -60,9 +60,9 @@ components: - write - program_counter - name: Integer registers - type: int_registers + type: int double_precision: false - elements: + registers: - name: - x0 - zero @@ -400,9 +400,9 @@ components: - read - write - name: Floating point registers - type: fp_registers + type: float double_precision: true - elements: + registers: - name: - f0 - ft0 @@ -738,7 +738,7 @@ components: - name: Vectorial registers type: v_registers double_precision: true - elements: + registers: - name: - v0 - vt0 @@ -1062,7 +1062,7 @@ components: - name: Control state registers type: csr_registers double_precision: false - elements: + registers: # USER registers - name: - ustatus @@ -2759,7 +2759,9 @@ instructions: - field: funct3 value: "110" definition: | - registers[rd] = registers[rs1] % registers[rs2]; + registers[rd] = CAPI.FP.int2uint( + CAPI.FP.uint2int(registers[rs1]) % CAPI.FP.uint2int(registers[rs2]) + ); help: Perform an XLEN-bit by XLEN-bit signed integer reminder of rs1 by rs2. - name: remu diff --git a/architecture/Z80.yml b/architecture/Z80.yml index e4216976d..1f340bdcb 100644 --- a/architecture/Z80.yml +++ b/architecture/Z80.yml @@ -20,11 +20,11 @@ config: - name: "RASM" description: "RASM Z80 Assembler" -components: +register_files: - name: Control registers - type: ctrl_registers + type: ctrl double_precision: false - elements: + registers: - name: - PC nbits: 16 @@ -36,9 +36,9 @@ components: - write - program_counter - name: Integer registers - type: int_registers + type: int double_precision: false - elements: + registers: - name: [A] nbits: 8 value: 0 diff --git a/architecture/simple8.yml b/architecture/simple8.yml index 74b1adf38..bab6bced3 100644 --- a/architecture/simple8.yml +++ b/architecture/simple8.yml @@ -25,11 +25,11 @@ templates: stopbit: 0 order: 0 -components: +register_files: - name: Control registers - type: ctrl_registers + type: ctrl double_precision: false - elements: + registers: - name: - PC nbits: 8 @@ -41,9 +41,9 @@ components: - write - program_counter - name: Integer registers - type: int_registers + type: int double_precision: false - elements: + registers: - name: - A encoding: 0 @@ -188,4 +188,4 @@ directives: size: 4 - name: .double action: double - size: 8 \ No newline at end of file + size: 8 diff --git a/creator-assembler b/creator-assembler index 0531a2707..2b4e4c1bf 160000 --- a/creator-assembler +++ b/creator-assembler @@ -1 +1 @@ -Subproject commit 0531a2707011af39e85d78ffd588d14c73861ffd +Subproject commit 2b4e4c1bfb35e016020c3a1139b67e92035027e7 diff --git a/docs/RISC-V Reference Guide.docx b/docs/RISC-V Reference Guide.docx deleted file mode 100644 index 45a3c9b87..000000000 Binary files a/docs/RISC-V Reference Guide.docx and /dev/null differ diff --git a/docs/chip.psd b/docs/chip.psd deleted file mode 100644 index a46ec2bef..000000000 Binary files a/docs/chip.psd and /dev/null differ diff --git a/docs/logos.psd b/docs/logos.psd deleted file mode 100644 index b9103a777..000000000 Binary files a/docs/logos.psd and /dev/null differ diff --git a/docs/schema/architecture.json b/docs/schema/architecture.json index 0c4a102b0..cc49f8269 100644 --- a/docs/schema/architecture.json +++ b/docs/schema/architecture.json @@ -5,7 +5,7 @@ "description": "v2", "type": "object", "required": [ - "components", + "register_files", "config", "instructions", "memory_layout", @@ -17,15 +17,15 @@ "description": "Architecture version", "type": "string" }, - "components": { - "description": "Components (register files) of the architecture. It's assumed that the first register of the first file will contain the program counter", + "register_files": { + "description": "Register files of the architecture", "type": "array", "items": { - "$ref": "#/definitions/Component" + "$ref": "#/definitions/RegisterFile" } }, "config": { - "description": "Metadata about the architecture Order of elements is assumed to be name, bits, description, data format, memory alignment, main function, passing convention, and sensitive register name", + "description": "Metadata about the architecture", "allOf": [ { "$ref": "#/definitions/Config" @@ -82,7 +82,7 @@ ] }, "memory_layout": { - "description": "Memory layout of the architecture. Order of elements is assumed to be optionally ktext start/end and kdata start/end, followed by text start/end, data start/end, and stack start/end", + "description": "Memory layout of the architecture", "allOf": [ { "$ref": "#/definitions/MemoryLayout" @@ -154,16 +154,16 @@ } ] }, - "Component": { + "RegisterFile": { "description": "Register file", "type": "object", - "required": ["double_precision", "elements", "name", "type"], + "required": ["double_precision", "registers", "name", "type"], "properties": { "double_precision": { "description": "Whether the registers have double the word size", "type": "boolean" }, - "elements": { + "registers": { "description": "Registers in this file", "type": "array", "items": { @@ -178,29 +178,29 @@ "description": "Type of the registers", "allOf": [ { - "$ref": "#/definitions/ComponentType" + "$ref": "#/definitions/RegisterType" } ] } } }, - "ComponentType": { + "RegisterType": { "description": "Types of register files allowed", "oneOf": [ { "description": "Control registers", "type": "string", - "enum": ["ctrl_registers"] + "enum": ["ctrl"] }, { "description": "Integer registers", "type": "string", - "enum": ["int_registers"] + "enum": ["int"] }, { "description": "Floating point registers", "type": "string", - "enum": ["fp_registers"] + "enum": ["float"] }, { "description": "Vector registers", diff --git a/docs/vue-tricks.md b/docs/vue-tricks.md index 8f12a99ef..e7077de28 100644 --- a/docs/vue-tricks.md +++ b/docs/vue-tricks.md @@ -262,7 +262,7 @@ export const coreEvents = mitt() export function updateSomeData(indexComp, indexElem) { // ... update your data ... - data[indexComp].elements[indexElem].value = newValue + data[indexComp].registers[indexElem].value = newValue // Notify UI layers (CLI ignores, web UI listens) coreEvents.emit("data-updated", { indexComp, indexElem }) @@ -394,4 +394,4 @@ export default defineComponent({ return { stuff: null as MyType | null } } }) -``` \ No newline at end of file +``` diff --git a/examples/RISCV-32-devices/example2.s b/examples/RISCV-32-devices/example2.s index 016e545be..401545fe7 100644 --- a/examples/RISCV-32-devices/example2.s +++ b/examples/RISCV-32-devices/example2.s @@ -27,7 +27,7 @@ # read int li t2, 5 sw t2, 0(t1) - lw t3, 0(t0) # t3: lenght + lw t3, 0(t0) # t3: length # print "Insert string..." la t2, string2 diff --git a/examples/RISCV-32-interrupts/example1.s b/examples/RISCV-32-interrupts/example1.s index acfd0e895..bd4c25611 100644 --- a/examples/RISCV-32-interrupts/example1.s +++ b/examples/RISCV-32-interrupts/example1.s @@ -30,3 +30,4 @@ ecall li t0, 0 + jr ra diff --git a/examples/RISCV-32-interrupts/example2.s b/examples/RISCV-32-interrupts/example2.s index bb9e1774b..08659c4c1 100644 --- a/examples/RISCV-32-interrupts/example2.s +++ b/examples/RISCV-32-interrupts/example2.s @@ -1,10 +1,12 @@ .data + console_ctrl_addr: .word 0xF0000000 + console_data_addr: .word 0xF0000008 .text rti: # load mcause to t0 - csrrw t0, MCAUSE, t0 - csrrw t1, MSCRATCH, t1 # swap t1 w/ mscratch + csrrw t0, mcause, t0 + csrrw t1, mscratch, t1 # swap t1 w/ mscratch # treat interruption @@ -15,15 +17,25 @@ rti: # load mcause to t0 rti_ecall: li t1, 1 beq a7, t1, rti_print_int -rti_print_int: print_int +rti_print_int: # load console data addr to t0 + la t0, console_data_addr + lw t0, 0(t0) + # load console ctrl addr to t1 + la t1, console_ctrl_addr + lw t1, 0(t1) + + sw a0, 0(t0) # store value in console data + + li t0, 1 + sw t0, 0(t1) # signal device to write an integer j rti_end -rti_end: csrrw t0, MCAUSE, t0 # restore t0 - csrrw t1, MSCRATCH, t1 # restore t1 +rti_end: csrrw t0, mcause, t0 # restore t0 + csrrw t1, mscratch, t1 # restore t1 mret main: li a7, 1 li a0, 69 ecall - jr ra # TODO: Implement proper exit \ No newline at end of file + jr ra diff --git a/examples/RISCV-64-interrupts/example1.s b/examples/RISCV-64-interrupts/example1.s index acfd0e895..bd4c25611 100644 --- a/examples/RISCV-64-interrupts/example1.s +++ b/examples/RISCV-64-interrupts/example1.s @@ -30,3 +30,4 @@ ecall li t0, 0 + jr ra diff --git a/examples/RISCV-64-interrupts/example2.s b/examples/RISCV-64-interrupts/example2.s index bb9e1774b..08659c4c1 100644 --- a/examples/RISCV-64-interrupts/example2.s +++ b/examples/RISCV-64-interrupts/example2.s @@ -1,10 +1,12 @@ .data + console_ctrl_addr: .word 0xF0000000 + console_data_addr: .word 0xF0000008 .text rti: # load mcause to t0 - csrrw t0, MCAUSE, t0 - csrrw t1, MSCRATCH, t1 # swap t1 w/ mscratch + csrrw t0, mcause, t0 + csrrw t1, mscratch, t1 # swap t1 w/ mscratch # treat interruption @@ -15,15 +17,25 @@ rti: # load mcause to t0 rti_ecall: li t1, 1 beq a7, t1, rti_print_int -rti_print_int: print_int +rti_print_int: # load console data addr to t0 + la t0, console_data_addr + lw t0, 0(t0) + # load console ctrl addr to t1 + la t1, console_ctrl_addr + lw t1, 0(t1) + + sw a0, 0(t0) # store value in console data + + li t0, 1 + sw t0, 0(t1) # signal device to write an integer j rti_end -rti_end: csrrw t0, MCAUSE, t0 # restore t0 - csrrw t1, MSCRATCH, t1 # restore t1 +rti_end: csrrw t0, mcause, t0 # restore t0 + csrrw t1, mscratch, t1 # restore t1 mret main: li a7, 1 li a0, 69 ecall - jr ra # TODO: Implement proper exit \ No newline at end of file + jr ra diff --git a/examples/RISCV-simple/example2.s b/examples/RISCV-simple/example2.s index b8147d5f2..146195b56 100644 --- a/examples/RISCV-simple/example2.s +++ b/examples/RISCV-simple/example2.s @@ -8,7 +8,8 @@ .text main: # 1.- to load float in hex form - lw s1, float1(x0) + la t0, float1 + lw s1, 0(t0) # 2.- to load masks # sign -> 1000 0000 0000 0000 ... @@ -20,7 +21,7 @@ main: # mant. -> 0000 0000 0111 1111 ... lui s7, 0x001F slli s7, s7, 16 - ori s0, x0, 0xFFFF + li s0, 0xFFFF or s7, s7, s0 # 3.- to apply mask diff --git a/examples/RISCV-simple/example3.s b/examples/RISCV-simple/example3.s index 624b8906b..3009a772c 100644 --- a/examples/RISCV-simple/example3.s +++ b/examples/RISCV-simple/example3.s @@ -8,7 +8,7 @@ .text main: # shift - lui a0, result1 + li a0, result1 lb a1, 0(a0) lh a2, 0(a0) lw a3, 0(a0) diff --git a/examples/RISCV-simple/example4.s b/examples/RISCV-simple/example4.s index b7af9a41d..cb60732ac 100644 --- a/examples/RISCV-simple/example4.s +++ b/examples/RISCV-simple/example4.s @@ -5,14 +5,14 @@ .text main: # loop initialization - lui x1, 0 - lui x2, 5 - lui x3, 1 + lui t1, 0 + lui t2, 5 + lui t3, 1 # loop header - loop1: beq x1, x2, fin1 + loop1: beq t1, t2, fin1 # loop body - add x1, x1, x3 - beq x0, x0, loop1 + add t1, t1, t3 + beq t0, t0, loop1 fin1: jalr x0, 0(ra) diff --git a/examples/RISCV-simple/example5.s b/examples/RISCV-simple/example5.s index d7468c3f7..ef7fd22cc 100644 --- a/examples/RISCV-simple/example5.s +++ b/examples/RISCV-simple/example5.s @@ -55,8 +55,13 @@ f1: main: # counting (matrix, 2, 6) - lui a0, matrix - lui a1, 2 - lui a2, 6 + li a0, matrix + li a1, 2 + li a2, 6 + addi sp, sp, -4 + sw ra, 0(sp) jal ra, counting + lw ra, 0(sp) + addi sp, sp, 4 + jr ra diff --git a/sinclair.html b/sinclair.html index ca2a31344..5017e6017 100644 --- a/sinclair.html +++ b/sinclair.html @@ -543,7 +543,7 @@

Executed Instructions

function updateRegisterView() { try { const registers = - creator.getRegistersByBank("int_registers").elements; + creator.getRegistersByBank("int").registers; let regText = ""; registers.forEach((reg, index) => { const name = reg.name[0].padEnd(4, " "); diff --git a/src/cli/commands/registers.mts b/src/cli/commands/registers.mts index bac2deea9..38dde3416 100644 --- a/src/cli/commands/registers.mts +++ b/src/cli/commands/registers.mts @@ -48,15 +48,15 @@ function displayRegistersByBank(regType: string, format: string = "raw"): void { console.log(`${registerBank.name}:`); - const rowCount = Math.ceil(registerBank.elements.length / 4); + const rowCount = Math.ceil(registerBank.registers.length / 4); // Calculate max width for each column const maxWidths = [0, 0, 0, 0]; for (let row = 0; row < rowCount; row++) { for (let col = 0; col < 4; col++) { const index = row * 4 + col; - if (index < registerBank.elements.length) { - const reg = registerBank.elements[index]; + if (index < registerBank.registers.length) { + const reg = registerBank.registers[index]; const primaryName = reg!.name[0]; const altNames = reg!.name.slice(1).join(","); const displayName = altNames @@ -71,8 +71,8 @@ function displayRegistersByBank(regType: string, format: string = "raw"): void { let line = ""; for (let col = 0; col < 4; col++) { const index = row * 4 + col; - if (index < registerBank.elements.length) { - const reg = registerBank.elements[index]; + if (index < registerBank.registers.length) { + const reg = registerBank.registers[index]; const primaryName = reg!.name[0]; const altNames = reg!.name.slice(1).join(","); @@ -82,7 +82,7 @@ function displayRegistersByBank(regType: string, format: string = "raw"): void { const rawValue = creator.dumpRegister( primaryName, - reg!.type === "fp_registers" ? "raw" : "twoscomplement", + reg!.type === "float" ? "raw" : "twoscomplement", ); const floatValue = creator.dumpRegister(primaryName, "decimal"); @@ -140,7 +140,7 @@ export function handleRegCommand(args: string[]): void { const rawValue = creator.dumpRegister( regName, - regInfo.type === "fp_registers" ? "raw" : "twoscomplement", + regInfo.type === "float" ? "raw" : "twoscomplement", ); const floatValue = creator.dumpRegister(regName, "decimal"); console.log(`${regName}: 0x${rawValue} | ${floatValue}`); diff --git a/src/cli/tutorial.mts b/src/cli/tutorial.mts index 634c5d15c..a2ce4c98a 100644 --- a/src/cli/tutorial.mts +++ b/src/cli/tutorial.mts @@ -185,9 +185,9 @@ const tutorialSteps: TutorialStep[] = [ }, { title: "Examining Registers", - text: "Registers are small, fast storage locations in the CPU. RISC-V has 32 general-purpose registers (x0-x31).\n\nTo view the integer registers, use the 'reg' command.\n\nTry it now by typing 'reg int_registers':", + text: "Registers are small, fast storage locations in the CPU. RISC-V has 32 general-purpose registers (x0-x31).\n\nTo view the integer registers, use the 'reg' command.\n\nTry it now by typing 'reg int':", waitForCommand: true, - expectedCommand: "reg int_registers", + expectedCommand: "reg int", executeAfter() { console.log( colorText( diff --git a/src/core/assembler/sailAssembler/web/CNAssambler.mjs b/src/core/assembler/sailAssembler/web/CNAssambler.mjs index d0a8ad000..53cad7cbc 100644 --- a/src/core/assembler/sailAssembler/web/CNAssambler.mjs +++ b/src/core/assembler/sailAssembler/web/CNAssambler.mjs @@ -391,13 +391,13 @@ export function writeDataDumpMemory32(){ main_memory.writeWord(BigInt(stack_address), [0x0, 0x0, 0x0, 0x0]); // writeMemory("00", parseInt(stack_address), "word") ; if (architecture.config.word_size == 32) { - architecture.components[1].elements[2].value = + architecture.register_files[1].registers[2].value = BigInt(parseInt(stack_address) >>> 0, 10); - architecture.components[1].elements[2].default_value = + architecture.register_files[1].registers[2].default_value = BigInt(parseInt(stack_address) >>> 0, 10); }else { - architecture.components[1].elements[2].value = stack_address; - architecture.components[1].elements[2].default_value = stack_address; + architecture.register_files[1].registers[2].value = stack_address; + architecture.register_files[1].registers[2].default_value = stack_address; } } @@ -638,14 +638,14 @@ export function writeDataDumpMemory64(){ main_memory.writeWord(BigInt(stack_address), [0x0, 0x0, 0x0, 0x0]); // writeMemory("00", parseInt(stack_address), "word") ; if (architecture.config.word_size == 32) { - architecture.components[1].elements[2].value = + architecture.register_files[1].registers[2].value = BigInt(parseInt(stack_address) >>> 0, 10); - architecture.components[1].elements[2].default_value = + architecture.register_files[1].registers[2].default_value = BigInt(parseInt(stack_address) >>> 0, 10); }else { - architecture.components[1].elements[2].value = stack_address; - architecture.components[1].elements[2].default_value = stack_address; + architecture.register_files[1].registers[2].value = stack_address; + architecture.register_files[1].registers[2].default_value = stack_address; } } export async function as(files){ diff --git a/src/core/capi/arduino.mts b/src/core/capi/arduino.mts index 636934a9c..ee3ae258f 100644 --- a/src/core/capi/arduino.mts +++ b/src/core/capi/arduino.mts @@ -1,23 +1,22 @@ /** - * Copyright 2018-2025 Felix Garcia Carballeira, Alejandro Calderon Mateos, - * Diego Camarmas Alonso + * Copyright 2018-2026 CREATOR Team. * - * This file is part of CREATOR. + * This file is part of CREATOR. * - * CREATOR is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. + * CREATOR is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. * - * CREATOR is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with CREATOR. If not, see . + * CREATOR is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. * + * You should have received a copy of the GNU Lesser General Public License + * along with CREATOR. If not, see . */ + import * as hooks from "./arduino_functions.mts"; import { loadedCreatino } from "../core.mjs"; diff --git a/src/core/capi/arduino_functions.mts b/src/core/capi/arduino_functions.mts index f62388391..f0b3727cd 100644 --- a/src/core/capi/arduino_functions.mts +++ b/src/core/capi/arduino_functions.mts @@ -1,3 +1,22 @@ +/** + * Copyright 2018-2026 CREATOR Team. + * + * This file is part of CREATOR. + * + * CREATOR is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * CREATOR is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with CREATOR. If not, see . + */ + import { crex_findReg } from "../register/registerLookup.mjs"; import { packExecute } from "../utils/utils.mjs"; import { diff --git a/src/core/capi/memory.mts b/src/core/capi/memory.mts index 4c1978c63..146440b3a 100644 --- a/src/core/capi/memory.mts +++ b/src/core/capi/memory.mts @@ -247,7 +247,7 @@ export const MEM = { // Add stack hint if we're writing to the stack segment if (segment === "stack") { - const reg = REGISTERS[i]!.elements[j]!; + const reg = REGISTERS[i]!.registers[j]!; stackTracker.addHint(address, reg.name.join(",")); } diff --git a/src/core/capi/registers.mts b/src/core/capi/registers.mts index f27f1696f..5478c5d31 100644 --- a/src/core/capi/registers.mts +++ b/src/core/capi/registers.mts @@ -39,7 +39,7 @@ export const REG = { const reg = crex_findReg(name); if (reg.match) { const nbits = - architecture.components[reg.indexComp!]!.elements[ + architecture.register_files[reg.indexComp!]!.registers[ reg.indexElem! ]!.nbits; writeRegister( diff --git a/src/core/core.d.ts b/src/core/core.d.ts index 8956e86b5..f9e723374 100644 --- a/src/core/core.d.ts +++ b/src/core/core.d.ts @@ -20,7 +20,7 @@ /** * Deno doesn't fully support "sloppy imports" * (https://docs.deno.com/runtime/reference/cli/unstable_flags/#--unstable-sloppy-imports), - * which would make our lives easier by just writting in a `foo.ts` file: + * which would make our lives easier by just writing in a `foo.ts` file: * ```ts * import { architecture, status } from "@/core/core"; * ``` @@ -31,11 +31,11 @@ // TODO: extract this data from the assembler -type RegisterBank = { +type RegisterFile = { name: string; type: string; double_precision: boolean; - elements: Register[]; + registers: Register[]; }; type Register = { @@ -101,7 +101,7 @@ type MemoryLayout = { type Directive = { name: string; action: string }; -export declare const REGISTERS: RegisterBank[]; +export declare const REGISTERS: RegisterFile[]; type ArchitectureInterrupts = { handlers: { @@ -140,7 +140,7 @@ type Architecture = { }[]; }; memory_layout: MemoryLayout; - components: RegisterBank[]; + register_files: RegisterFile[]; instructions: Instruction[]; pseudoinstructions: PseudoInstruction[]; directives: Directive[]; diff --git a/src/core/core.mjs b/src/core/core.mjs index 4b281b26e..2341b38ac 100644 --- a/src/core/core.mjs +++ b/src/core/core.mjs @@ -94,7 +94,7 @@ export let WORDSIZE; /** @type {number} */ export let BYTESIZE; export let ENDIANNESSARR = []; -/** @type {import("./core.d.ts").RegisterBank[]} */ +/** @type {import("./core.d.ts").RegisterFile[]} */ export let REGISTERS; export const register_size_bits = 32; //TODO: load from architecture /** @type {Memory} */ @@ -188,8 +188,8 @@ export function loadArchitecture(architectureYaml, isa = []) { ENDIANNESSARR = endianness; } - REGISTERS = architecture.components; - status.pcRegisterNames = REGISTERS.flatMap(bank => bank.elements).find( + REGISTERS = architecture.register_files; + status.pcRegisterNames = REGISTERS.flatMap(bank => bank.registers).find( reg => reg.properties.includes("program_counter"), ).name; crex_clearRegisterCache(); @@ -374,7 +374,7 @@ export function reset() { // reset registers // Restore register default values for (const file of REGISTERS) { - for (const register of file.elements) { + for (const register of file.registers) { register.value = register.default_value } } @@ -604,7 +604,7 @@ export function dumpRegister(register, format = "hex") { const result = crex_findReg(register); const registerSize = - REGISTERS[result.indexComp].elements[result.indexElem].nbits; + REGISTERS[result.indexComp].registers[result.indexElem].nbits; if (result.match === 1) { if (format === "hex") { @@ -619,7 +619,7 @@ export function dumpRegister(register, format = "hex") { return twosComplement; } else if (format === "raw") { const value = - REGISTERS[result.indexComp].elements[ + REGISTERS[result.indexComp].registers[ result.indexElem ].value.toString(16); return value; @@ -632,44 +632,29 @@ export function dumpRegister(register, format = "hex") { } export function getRegisterTypes() { - // Extract unique register types from architecture components - const registerTypes = REGISTERS.filter(component => - component.type.includes("registers"), - ).map(component => component.type); + // Extract unique register types from architecture register files + const registerTypes = REGISTERS.map(file => file.type); return registerTypes; } export function getRegistersByBank(regType) { - // Find the component with the specified register type - const component = REGISTERS.find(comp => comp.type === regType); - - if (!component) { - return null; - } - - return { - name: component.name, - type: component.type, - elements: component.elements, - double_precision: component.double_precision, - double_precision_type: component.double_precision_type, - }; + // Find the register file with the specified register type + const file = REGISTERS.find(comp => comp.type === regType); + return file? file : null; } export function getRegisterInfo(regName) { - // Find the register in all components - for (const component of REGISTERS) { - if (component.type.includes("registers")) { - for (const element of component.elements) { - // Check if this register matches by any of its names - if (element.name.includes(regName)) { - return { - ...element, - type: component.type, - nbits: element.nbits, - }; - } + // Find the register in all register files + for (const file of REGISTERS) { + for (const element of file.registers) { + // Check if this register matches by any of its names + if (element.name.includes(regName)) { + return { + ...element, + type: file.type, + nbits: element.nbits, + }; } } } diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index a9857c6aa..181496b03 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -123,7 +123,7 @@ export function kbd_read_float(keystroke, params) { // If the current architecture has a write float specialization, use it. // Otherwise, fallback to writing the bits directly if (CAPI.ARCH.writeFloat !== undefined) { - const reg = architecture.components[params.indexComp].elements[params.indexElem] + const reg = architecture.register_files[params.indexComp].registers[params.indexElem] CAPI.ARCH.writeFloat(value, reg.name[0]) } else { const buffer = new ArrayBuffer(4); @@ -157,7 +157,7 @@ export function kbd_read_double(keystroke, params) { // If the current architecture has a write float specialization, use it. // Otherwise, fallback to writing the bits directly if (CAPI.ARCH.writeDouble !== undefined) { - const reg = architecture.components[params.indexComp].elements[params.indexElem] + const reg = architecture.register_files[params.indexComp].registers[params.indexElem] CAPI.ARCH.writeDouble(value, reg.name[0]) } else { const buffer = new ArrayBuffer(8); diff --git a/src/core/executor/decoder.mjs b/src/core/executor/decoder.mjs index a1b3be9bb..0922532dd 100644 --- a/src/core/executor/decoder.mjs +++ b/src/core/executor/decoder.mjs @@ -36,7 +36,7 @@ export function resetDecoderCache() { /** * Returns the register name given its binary representation and type * - * @param {string} type - The register type (e.g., "int_registers", "fp_registers", "ctrl_registers") + * @param {string} type - The register type (e.g., "int", "float", "ctrl") * @param {string} binaryValue - The binary representation of the register * @returns {string|null} - The register name or null if not found */ @@ -48,7 +48,7 @@ function decodeRegister(type, binaryValue) { continue; } - for (const register of component.elements) { + for (const register of component.registers) { if (register.encoding === binaryValueInt) { return register.name[0]; // Return the first name (canonical) } @@ -139,14 +139,14 @@ function processInstructionField(field, encodedInstruction) { // The register type in the instruction is different from the one in the architecture switch (field.type) { case "INT-Reg": - convertedType = "int_registers"; + convertedType = "int"; break; case "SFP-Reg": case "DFP-Reg": - convertedType = "fp_registers"; + convertedType = "float"; break; case "Ctrl-Reg": - convertedType = "ctrl_registers"; + convertedType = "ctrl"; break; default: throw new Error("Unknown register type: " + field.type); diff --git a/src/core/executor/executor.mjs b/src/core/executor/executor.mjs index 577ca2f90..be6f43100 100644 --- a/src/core/executor/executor.mjs +++ b/src/core/executor/executor.mjs @@ -221,7 +221,7 @@ function incrementProgramCounter(nwords) { const increment = BigInt((nwords * WORDSIZE) / BYTESIZE); // Direct access to PC register value const pc_element = - REGISTERS[PC_REG_INDEX.indexComp].elements[PC_REG_INDEX.indexElem]; + REGISTERS[PC_REG_INDEX.indexComp].registers[PC_REG_INDEX.indexElem]; const new_pc = BigInt(pc_element.value) + increment; guiVariables.previous_PC = BigInt(pc_element.value); diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js index d801f29b1..1de2573c7 100644 --- a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js +++ b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js @@ -840,21 +840,21 @@ var Module = (() => { // console.log("Tamaño: ", size_elem); if(size_elem === "000"){ document.app.$data.v_length = 8; - // architecture.components[3].total_elements = 64; + // architecture.register_files[3].total_elements = 64; } else if (size_elem === "001") { document.app.$data.v_length = 16; - // architecture.components[3].total_elements = 32; + // architecture.register_files[3].total_elements = 32; } else if (size_elem === "010"){ document.app.$data.v_length = 32; - // architecture.components[3].total_elements = 16; + // architecture.register_files[3].total_elements = 16; }else { document.app.$data.v_length = 64; - // architecture.components[3].total_elements = 8; + // architecture.register_files[3].total_elements = 8; } - // architecture.components[3].length_elem = length_vext; + // architecture.register_files[3].length_elem = length_vext; } else if (CSRMatch[2] === "vl"){ - // architecture.components[3].elems_op = parseInt(CSRMatch[5], 16); + // architecture.register_files[3].elems_op = parseInt(CSRMatch[5], 16); } } if (vectorMatch){ diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js index 650cf91e2..4b14928ee 100644 --- a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js +++ b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js @@ -604,24 +604,24 @@ var Module = (() => { // console.log("Tamaño: ", size_elem); if(size_elem === "000"){ document.app.$data.v_length = 8; - // architecture.components[3].total_elements = 64; + // architecture.register_files[3].total_elements = 64; } else if (size_elem === "001") { document.app.$data.v_length = 16; // length_vext = 16; - // architecture.components[3].total_elements = 32; + // architecture.register_files[3].total_elements = 32; } else if (size_elem === "010"){ document.app.$data.v_length = 32; // length_vext = 32; - // architecture.components[3].total_elements = 16; + // architecture.register_files[3].total_elements = 16; }else { document.app.$data.v_length = 64; // length_vext = 64; - // architecture.components[3].total_elements = 8; + // architecture.register_files[3].total_elements = 8; } - // architecture.components[3].length_elem = length_vext; + // architecture.register_files[3].length_elem = length_vext; } else if (CSRMatch[2] === "vl"){ - // architecture.components[3].elems_op = parseInt(CSRMatch[5], 16); + // architecture.register_files[3].elems_op = parseInt(CSRMatch[5], 16); } } if (vectorMatch){ diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js b/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js index 1ba5bacf6..d1e78ac8b 100644 --- a/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js +++ b/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js @@ -619,24 +619,24 @@ var Module = (() => { if(size_elem === "000"){ document.app.$data.v_length = 8; // length_vext = 8; - // architecture.components[3].total_elements = 64; + // architecture.register_files[3].total_elements = 64; } else if (size_elem === "001") { document.app.$data.v_length = 16; // length_vext = 16; - // architecture.components[3].total_elements = 32; + // architecture.register_files[3].total_elements = 32; } else if (size_elem === "010"){ document.app.$data.v_length = 32; // length_vext = 32; - // architecture.components[3].total_elements = 16; + // architecture.register_files[3].total_elements = 16; }else { document.app.$data.v_length = 64; // length_vext = 64; - // architecture.components[3].total_elements = 8; + // architecture.register_files[3].total_elements = 8; } - // architecture.components[3].length_elem = length_vext; + // architecture.register_files[3].length_elem = length_vext; } else if (CSRMatch[2] === "vl"){ - // architecture.components[3].elems_op = parseInt(CSRMatch[5], 16); + // architecture.register_files[3].elems_op = parseInt(CSRMatch[5], 16); } } if (vectorMatch){ diff --git a/src/core/memory/StackTracker.mts b/src/core/memory/StackTracker.mts index 1843f23c3..923260931 100644 --- a/src/core/memory/StackTracker.mts +++ b/src/core/memory/StackTracker.mts @@ -87,7 +87,7 @@ export class StackTracker { private static getCurrentStackPointer(): number { // find stack pointer register const sp = REGISTERS.flatMap(bank => - bank.elements.filter(register => + bank.registers.filter(register => // check it has the stack pointer property register.properties.includes("stack_pointer"), ), diff --git a/src/core/register/registerGlowState.mjs b/src/core/register/registerGlowState.mjs index 7d43a9e67..d9629f173 100644 --- a/src/core/register/registerGlowState.mjs +++ b/src/core/register/registerGlowState.mjs @@ -24,7 +24,7 @@ */ // Set of register keys that should be glowing -// Key format: "bankIndex:registerIndex" (e.g., "0:5" for REGISTERS[0].elements[5]) +// Key format: "bankIndex:registerIndex" (e.g., "0:5" for REGISTERS[0].registers[5]) const glowingRegisters = new Set(); /** diff --git a/src/core/register/registerLookup.mjs b/src/core/register/registerLookup.mjs index 4b3f71c63..28fe315d8 100644 --- a/src/core/register/registerLookup.mjs +++ b/src/core/register/registerLookup.mjs @@ -54,8 +54,8 @@ export function crex_findReg(value1) { } for (let i = 0; i < REGISTERS.length; i++) { - for (let j = 0; j < REGISTERS[i].elements.length; j++) { - if (REGISTERS[i].elements[j].name.includes(value1) !== false) { + for (let j = 0; j < REGISTERS[i].registers.length; j++) { + if (REGISTERS[i].registers[j].name.includes(value1) !== false) { ret.match = 1; ret.indexComp = i; ret.indexElem = j; @@ -86,9 +86,9 @@ export function crex_findReg_bytag(value1) { } for (let i = 0; i < REGISTERS.length; i++) { - for (let j = 0; j < REGISTERS[i].elements.length; j++) { + for (let j = 0; j < REGISTERS[i].registers.length; j++) { if ( - REGISTERS[i].elements[j].properties.includes(value1) !== false + REGISTERS[i].registers[j].properties.includes(value1) !== false ) { ret.match = 1; ret.indexComp = i; diff --git a/src/core/register/registerOperations.mjs b/src/core/register/registerOperations.mjs index be6d578b9..00823d4af 100644 --- a/src/core/register/registerOperations.mjs +++ b/src/core/register/registerOperations.mjs @@ -52,7 +52,7 @@ export function readRegister(indexComp, indexElem) { }; if ( - REGISTERS[indexComp].elements[indexElem].properties.includes("read") !== + REGISTERS[indexComp].registers[indexElem].properties.includes("read") !== true ) { for (let i = 0; i < instructions.length; i++) { @@ -63,25 +63,25 @@ export function readRegister(indexComp, indexElem) { throw packExecute( true, "The register " + - REGISTERS[indexComp].elements[indexElem].name.join(" | ") + + REGISTERS[indexComp].registers[indexElem].name.join(" | ") + " cannot be read", "danger", null, ); } - return BigInt(REGISTERS[indexComp].elements[indexElem].value); + return BigInt(REGISTERS[indexComp].registers[indexElem].value); } /** - * Writes the specified value in the specified register, given its component and - * index elements + * Writes the specified value in the specified register, given its register file and + * register indexes * * @param {bigint} value Value to write - * @param {number} indexComp Index of the component/bank - * @param {number} indexElem Index of the element + * @param {number} indexFile Index of the component/bank + * @param {number} indexReg Index of the element */ -export function writeRegister(value, indexComp, indexElem) { +export function writeRegister(value, indexFile, indexReg) { const draw = { space: [], info: [], @@ -103,8 +103,8 @@ export function writeRegister(value, indexComp, indexElem) { throw new Error("Called writeRegister with a number, not BigInt"); } - const component = REGISTERS[indexComp]; - const element = component.elements[indexElem]; + const component = REGISTERS[indexFile]; + const element = component.registers[indexReg]; const properties = element.properties; const elementName = element.name.join(" | "); const stackStart = architecture.memory_layout.stack.start; @@ -123,7 +123,7 @@ export function writeRegister(value, indexComp, indexElem) { } element.value = value; - sentinel.recordRegisterWrite(indexComp, indexElem); + sentinel.recordRegisterWrite(indexFile, indexReg); if (properties.includes("stack_pointer") && value !== stackStart) { writeStackLimit(value); @@ -133,9 +133,9 @@ export function writeRegister(value, indexComp, indexElem) { // check if in RISC-V Sail has to be glowed the register by instruction execution if (architecture.config.name.includes("SRV")){ if (userMode32 || userMode64 || userMode32vd) - notifyRegisterUpdate(indexComp, indexElem); + notifyRegisterUpdate(indexFile, indexReg); }else - notifyRegisterUpdate(indexComp, indexElem); + notifyRegisterUpdate(indexFile, indexReg); } } diff --git a/src/core/sentinel/sentinel.mts b/src/core/sentinel/sentinel.mts index ef0a0ab0a..4ca881f2d 100644 --- a/src/core/sentinel/sentinel.mts +++ b/src/core/sentinel/sentinel.mts @@ -59,7 +59,7 @@ class RegisterEvent { get registerName() { return ( - REGISTERS[this.regIndex]!.elements[this.elemIndex]!.name + REGISTERS[this.regIndex]!.registers[this.elemIndex]!.name ); } @@ -91,7 +91,7 @@ class CallFrame { const values: bigint[][] = []; for (const file of REGISTERS) { const curr = []; - for (const reg of file.elements) { + for (const reg of file.registers) { curr.push(reg.value); } values.push(curr); @@ -155,7 +155,7 @@ class ConventionRules { elemIndex: number ): SentinelErrorData[] { const violations = []; - const register = REGISTERS[regIndex]!.elements[elemIndex]!; + const register = REGISTERS[regIndex]!.registers[elemIndex]!; const events = frame.getRegisterEvents(regIndex, elemIndex); // Rule 1: Saved registers must be saved before modification @@ -322,7 +322,7 @@ class CallingConventionValidator { // Validate each saved register for (const [i, file] of REGISTERS.entries()) { - for (const [j, register] of file.elements.entries()) { + for (const [j, register] of file.registers.entries()) { // Only check registers that should be saved if (register.properties.includes("saved")) { const regViolations = ConventionRules.validateSavedRegister( diff --git a/src/core/utils/architectureProcessor.mjs b/src/core/utils/architectureProcessor.mjs index 053942d07..db1af34a8 100644 --- a/src/core/utils/architectureProcessor.mjs +++ b/src/core/utils/architectureProcessor.mjs @@ -413,16 +413,16 @@ function processPseudoInstructions(architectureObj) { * @returns {Object} - The architecture object with converted values */ function convertElementValuesToBigInt(architectureObj) { - if (!architectureObj.components) { + if (!architectureObj.register_files) { return architectureObj; } - for (const component of architectureObj.components) { - if (!component.elements) { + for (const file of architectureObj.register_files) { + if (!file.registers) { continue; } - for (const element of component.elements) { + for (const element of file.registers) { // Convert function using two's complement const convert = (x) => BigInt.asUintN(element.nbits, BigInt(x)); // Convert value to BigInt if it exists and is not already a BigInt diff --git a/src/debug/runner.mts b/src/debug/runner.mts index da614114c..0c8f5cf0c 100644 --- a/src/debug/runner.mts +++ b/src/debug/runner.mts @@ -153,11 +153,11 @@ async function main() { // console.log( // `Breakpoint hit at PC = 0x${breakpoint.toString(16).padStart(4, "0").toUpperCase()}`, // ); - // // for each element in in creator.getRegistersByBank("int_registers").elements, print: + // // for each element in in creator.getRegistersByBank("int").registers, print: // // name[0], value // creator - // .getRegistersByBank("int_registers") - // .elements.forEach(reg => { + // .getRegistersByBank("int") + // .registers.forEach(reg => { // console.log( // `${reg.name[0]}: 0x${reg.value.toString(16)}`, // ); @@ -170,8 +170,8 @@ async function main() { } if (totalInstructions === 0) { creator - .getRegistersByBank("int_registers")! - .elements.forEach(reg => { + .getRegistersByBank("int")! + .registers.forEach(reg => { console.log( ` ${reg.name[0]}: 0x${reg.value.toString(16)}`, ); @@ -180,8 +180,8 @@ async function main() { const ret = step(); // if (totalInstructions > 0) { // creator - // .getRegistersByBank("int_registers") - // .elements.forEach(reg => { + // .getRegistersByBank("int") + // .registers.forEach(reg => { // console.log( // ` ${reg.name[0]}: 0x${reg.value.toString(16)}`, // ); @@ -200,9 +200,9 @@ async function main() { ret.instructionData.machineCode, ); // Dump registers after each cycle on one line - const regBank = creator.getRegistersByBank("int_registers"); + const regBank = creator.getRegistersByBank("int"); if (regBank) { - const registers = regBank.elements.map( + const registers = regBank.registers.map( reg => `${reg.name[0]}:0x${reg.value.toString(16)}`, ); console.log(registers.join(" ")); diff --git a/src/rpc/server.mts b/src/rpc/server.mts index 848a619c2..3fbe83329 100644 --- a/src/rpc/server.mts +++ b/src/rpc/server.mts @@ -426,7 +426,7 @@ class CreatorRpcServer { }; } - const registers = registerBank.elements.map(reg => { + const registers = registerBank.registers.map(reg => { // Create display name with primary and alternative names const primaryName = reg.name[0]; const alternativeNames = reg.name.slice(1); diff --git a/src/web/App.vue b/src/web/App.vue index 60ec9a6bc..8bf935a58 100644 --- a/src/web/App.vue +++ b/src/web/App.vue @@ -313,7 +313,7 @@ export default { // we must store this data in the root, bc it resets when re-mounting a // component (in this case, RegisterFile) - data_mode: "int_registers", + data_mode: "int", reg_name_representation: "all", memory_segment: "data", diff --git a/src/web/arduino/pinstates.mts b/src/web/arduino/pinstates.mts index 0b2c23158..536259e2d 100644 --- a/src/web/arduino/pinstates.mts +++ b/src/web/arduino/pinstates.mts @@ -1,3 +1,22 @@ +/** + * Copyright 2018-2026 CREATOR Team. + * + * This file is part of CREATOR. + * + * CREATOR is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * CREATOR is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with CREATOR. If not, see . + */ + import { ref, type Ref } from "vue"; import { coreEvents, type ArduinoPinRead } from "@/core/events.mts"; // --- Tipado --- diff --git a/src/web/components/ArchitectureView.vue b/src/web/components/ArchitectureView.vue index 2eb25c016..99fadd56e 100644 --- a/src/web/components/ArchitectureView.vue +++ b/src/web/components/ArchitectureView.vue @@ -251,7 +251,7 @@ export default defineComponent({
- +
diff --git a/src/web/components/SimulatorView.vue b/src/web/components/SimulatorView.vue index 887ad2b60..0522bfb3d 100644 --- a/src/web/components/SimulatorView.vue +++ b/src/web/components/SimulatorView.vue @@ -146,7 +146,7 @@ export default defineComponent({ .