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<br/><br/>

<p><img src="img/openasip-logo-160x160.png" alt="OpenASIP logo" style="float:left; margin-right: 10px;">OpenASIP (formerly TTA-based Co-design Environment or TCE) is an <i>open application-specific instruction-set toolset</i>. It can be used to design and program customized compiler-programmable accelerators based on the energy efficient <b>Transport Triggered Architecture</b> (TTA) processor template. Starting from OpenASIP 2.0, it can be also used for RISC-V instruction-set co-design.
<br/><br/>
The toolset provides a complete retargetable co-design
flow from high-level language programs down to synthesizable processor
RTL (VHDL and Verilog backends supported) and parallel program binaries.
Processor customization points include the register files, function units,
supported operations, and the interconnection network.</p>

<br/><br/>
<br/><br/>

<p align="center"><a href="img/openasip_design_flow.png"><img src=img/openasip_design_flow.png id="flow" /></a></p>

<p>OpenASIP development is led by the <b>Customized Parallel Computing</b> (<a href="http://www.tuni.fi/cpc">CPC</a>)
group at the
<a href="http://www.tuni.fi/">Tampere University</a>, <a href="http://finland.fi">Finland</a>. Further reading:
  <a href="http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html">
    LLVM project blog post about OpenASIP</a>.</p>

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          <h1>News and updates</h1>

          <div class="news-headline">
            March 13th, 2026: <a href="https://github.com/cpc/openasip/releases/tag/v2.2">OpenASIP 2.2</a> released!</div>

          <p>New in this release is support for LLVM versions 21 and 22, various fixes for building and running the tools on Ubuntu 24.04 LTS, automated RISC-V custom instruction compiler retargeting, CV-X and ROCC interface support for SFU generation, an automated design space exploration flow (AEx), among others.  See the
            <a href="https://github.com/cpc/openasip/releases/tag/v2.2">release notes</a>
            for more details.</p>
            <p>Install instructions can be found in the <a href="https://github.com/cpc/openasip/tree/openasip-2.2?tab=readme-ov-file#installing-prerequisities">README</a>.
          </p>

        <div class="news-headline">
            <a id="ntnu-asip"></a>
            November 18th, 2024: OpenASIP used for a customized processor for medical ultrasound beamforming by an NTNU researcher
          </div>
          <p>
            A <a href="https://ntnuopen.ntnu.no/ntnu-xmlui/handle/11250/3156426">master's thesis</a> utilizing OpenASIP for the design and programming of an ASIP for medical ultrasound beamforming was published by NTNU. The author demonstrates the benefits of ASIPs by combining instruction set customization and interconnection pruning, yielding promising results in terms of performance, area, and power consumption compared to both OpenASIP-designed baseline processors and related work.

            We were happy to see that this design didn’t fall into the common pitfall of TTA designs with a lot of redundant datapath connections. Fully connected buses have been sadly very popular in designs done outside the group - we blame the too easy-to-use “fully connect IC” functionality in the Processor Designer for that! Unfortunately the IC in this design was so heavily optimized that the C compiler couldn’t produce efficient code and the best results were only received via hand coding the processor – something for the future code generation research to improve upon.

            <a href="https://ntnuopen.ntnu.no/ntnu-xmlui/handle/11250/3156426"><img class="img-responsive img-centered" width="600px" src=img/ntnu_2024_msc_thesis_beamforming.png id="flow" /></a>
              Picture from: Gustav Kollstrøm, "Application-Specific Instruction Set Processor for Medical Ultrasound Beamforming", master's thesis, NTNU, 2024
          </p>

          <div class="news-headline">
            April 10th, 2024: OpenASIP enables R-Blocks, a compiler-programmable CGRA
          </div>
          <p>
            As a result of collaboration between Eindhoven University of Technology, Netherlands and Tampere University, Finland, the work on R-Blocks, an ultra low power coarse-grained reconfigurable array CGRA was published in ACM Transactions on Reconfigurable Technology and Systems (TRETS). CGRAs have been proposed as a flexible yet energy-efficient platform. Thanks to OpenASIP's flexible architecture description template and retargetable compiler, R-Blocks is the first compiler-programmable CGRA. Read the publication <a href="https://research.tue.nl/en/publications/r-blocks-an-energy-efficient-flexible-and-programmable-cgra">here</a>.
            <a href="https://pure.tue.nl/ws/portalfiles/portal/323956010/RBlocks_journal_preprint.pdf"><img class="img-responsive img-centered" width="600px" src=img/r-blocks-cgra.png id="flow" /></a>
          </p>

          <div class="news-headline">
            February 16th, 2024: OpenASIP-based RISC-V function unit generation from Gebze Technical University</div>
          <p>
            In a recent work Yanık et al. used OpenASIP toolset as a basis for rapidly extending the instruction set of RISC-V cores. They use Vitis HLS tool to generate custom function units (FU) directly from C program descriptions. What a great idea! The user needs to only give the description of the custom operation in C and the tools generate a full function unit out of it. After that, their scripts integrate the function unit into a RISC-V ASIP using OpenASIP. It’s great to see how our easy-to-use custom FU integration enables people to create experiments like this.
Their paper DELTA-V: An Open-Source High-Level Synthesis Driven ASIP Design Automation Tool for RISC-V Microprocessors was published in 2023 14th International Conference on Electrical and Electronics Engineering (ELECO). The paper is available <a href="https://doi.org/10.1109/ELECO60389.2023.10416066"> here</a> and the source code <a href="https://github.com/DELTAICLAB/DELTA-V"> here</a>.
          </p>

          <div class="news-headline">
            December 20th, 2023: <a href="https://github.com/cpc/openasip/tree/openasip-2.1/openasip">OpenASIP 2.1</a> released!</div>

          <p>A new version of OpenASIP released! See the
            <a href="https://github.com/cpc/openasip/blob/openasip-2.1/openasip/CHANGES">change summary</a>
            for more details. Install instructions can be found in the <a href="https://github.com/cpc/openasip/blob/openasip-2.1/README.md">README</a>.
          </p>

          <div class="news-headline">
            December 11th, 2023: OpenASIP-designed audio coprocessor
            from University of Turin</div>

          <p>Interesting audio processor case study designed with OpenaASIP was
            published by University of Turin researchers who received good
            results even while using a fully connected interconnection matrix:
            The power consumption of the developed TTA architecture was found
            to be significantly lower compared to traditional software-based
            approaches, with a total estimated power of approximately 350 mW.
            Details can be found in the
            <a href="https://ieeexplore.ieee.org/document/10335333">publication</a>
            and the
            <a href="https://webthesis.biblio.polito.it/26860/">master's thesis</a>.
          </p>

          <div class="news-headline">
            <a href="release_2_0.html">November 23rd, 2022: OpenASIP 2.0 released!</a></div>

          <p>The first OpenASIP version with preliminary RISC-V customization support is now out!</p>

          <div class="news-headline">
            July 23rd, 2018: A tutorial slide deck with clickable videos uploaded</div>

          <p>The <a href="slides/2018-06-OpenASIP-Tour-with-Clickable-Videos.pptx">slide set</a> (39M)
            contains clickable videos and goes through most of the tool set. It was first presented
            in OpenSuco 3 workshop organized within the ISC High Performance 2018 conference (June 28th in Frankfurt, Germany). </p>

        </div>

        <div class="news-headline">
          <a name="pervasive"></a>
            October 4th, 2017: OpenASIP-based demo featured on the lab's blog</div>

        <p>A demonstration featuring a neural network coprocessor designed with OpenASIP
          was shown at CIVIT.</p>

        <p>For more info, read the post on the
          <a href="https://pervasive.cs.tut.fi/?p=2060">Pervasive Computing blog</a>.</p>

          <div class="news-headline">
          <a href="https://tuni.fi/cpc/old_news.html">older news on CPC group's website</a>
            </div>

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          <h1>Feature highlights</h1>

          <ul>
            <li>Compiler:
              <ul>
                <li><a href="http://llvm.org">LLVM</a> based, Clang as the default frontend</li>
                <li>OpenCL support via the <a href="http://portablecl.org">pocl</a> project</li>
                <li>Basic block instruction scheduler (top-down and bottom-up)</li>
                <li>Delay slot filling</li>
                <li>Software bypassing</li>
                <li>(experimental) Operand sharing</li>
                <li>Custom operation support </li>
                <li>Parallel TTA assembler</li>
                <li>Software and hardware floating point support</li>
                <li>Basic debugging info support</li>
                <li>Multiple address space support</li>
                <li>Support for native computation on half precision floats (fp16)</li>
              </ul>
            </li>
            <li>Simulator:
              <ul>
                <li>Graphical and command line user interfaces</li>
                <li>Interpretive debugging engine for cycle stepping</li>
                <li>Static compiled engine for fast simulation with basic block
                  granularity (but cycle count accuracy)</li>
                <li>Dynamic compiled engine for improved startup time with fast simulation</li>
                <li>SystemC integration API</li>
              </ul>
            </li>
            <li>Processor and Program Image Generation:
              <ul>
                <li>Support for generating implementation for the designed processor as VHDL. Experimental support for Verilog.</li>
                <li>Generates bit image of the program (supported formats include
                  the Altera MIF) </li>
                <li>Dictionary-based instruction compression</li>
                <li>Automated generation of the files needed to integrate the core to
                  different FPGA platforms.</li>
                <li>IP-XACT 1.5 support</li>
              </ul>
            </li>
            <li>Design space exploration:
              <ul>
                <li>Automated, manual and semi-automatic algorithm implementations</li>
                <li>Tools that allow easy modification of the target architecture</li>
                <li>Automated search of the connectivity design space</li>
              </ul>
            </li>
            <li>Integrated Development Environment tools:
              <ul>
                <li>Graphical user interface (GUI) for editing architecture resources</li>
                <li>GUI for editing operation set definitions </li>
              </ul>
            </li>
          </ul>
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