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<h1 class="section-heading">Customized Parallel<br /> Computing (CPC) group</h1>
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<p>
This is the home page of the CPC research group of Tampere University. The group's name in Finnish is Räätälöity rinnakkaislaskenta. CPC's main research focus is on design and programming methodologies of customized parallel computing platforms and real time implementations of challenging algorithms.
</p>
<br />
<p>
In addition to <a href="publications.html">publications</a> and theses listed here as academic contributions, CPC has also made major open source contributions in the field of portable and customized heterogeneous computing: The group has created <a href="http://openasip.org/">OpenASIP</a> and <a href="http://portablecl.org/">Portable Computing Language (pocl)</a> which are being used widely as research platforms and even for product use cases. CPC also created the prototype <a href="https://dl.acm.org/doi/10.1145/3388333.3388641">HIPCL</a> tool which evolved into <a href="https://github.com/CHIP-SPV/chipStar">chipStar</a>, a portable CUDA/HIP implementation using open standards.
</p>
<br />
<p>
An algorithm domain with extreme computational demands that CPC has been very interested in the past years is real time ray tracing. A separate focus group was formed for finding algorithmic, parallel/heterogeneous implementation and custom hardware solutions for its challenges in 2015. The group's web pages are <a href="http://www.tuni.fi/vga">here</a>.
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March 10th, 2026: <a href="https://trepo.tuni.fi/handle/10024/234994">chipStar journal article</a> published</div>
<p>chipStar is an open source software tool that enables building unmodified CUDA and HIP programs
into binaries that rely solely on open cross-vendor compute standards OpenCL and SPIR-V. The
origin of chipStar is the HIPCL tool developed in the CPC group, which was then refined to chipStar
in collaboration with Argonne, Intel and PGLC, among others.</p>
<p>The journal article discusses technical aspects of chipStar and the feature
mismatches between the CUDA/HIP APIs and OpenCL. It also proposes a set of standard extensions
to bridge the essential gaps in the future.</p>
<p>The key benefit of the tool is its portability, which is demonstrated by providing
performance evaluations on a diversity of less common CPU/GPU platforms including RISC-V/PowerVR
and ARM Mali.</p>
<p>chipStar is now considered mature enough
for wider testing and even production use, which is demonstrated by successful porting and competitive
performance of GAMESS-GPU-HF, a complex HPC application.</p>
<p>The article can be downloaded <a href="https://trepo.tuni.fi/handle/10024/234994">here</a>. The
source code repository of chipStar is in <a href="https://github.com/CHIP-SPV/chipStar/">github</a>.</p>
<p align="center">
<img src="img/2026-chipStar-article.png" border="0"
alt="chipStar journal article" width="500px" />
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November 6th, 2025: New <a href="publications.html">publication</a> added</div>
<p>
Verification and possible third-party certification is a time-consuming and cost-inducing part of designing digital IPs. In the case of customizable processors, modifying the instruction set of the processor is an intrusive process involving multiple stages of the processor pipeline. An approach to reducing or even removing the amount of verification and certification is using standardized coprocessor/accelerator interfaces. The interface is implemented into the processor only once, after which accelerator modules can be connected to the interface, allowing the verification and certification of the modules to be separated. In an extended journal article published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems we demonstrate how accelerators using RoCC and CV-X-IF standard interfaces for RISC-V can be generated from the same description leveraging the flexibility of OpenASIP's function unit generator. The article is available <a href="https://doi.org/10.1109/TVLSI.2025.3586902">here</a>.
</p>
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September 5th, 2025: <a href="https://doi.org/10.1177/10943420251369350">PoCL-R journal extension</a> published</div>
<p>
Modern mobile devices execute intensive tasks with limited compute resources. Offloading these tasks over networks to more capable devices such as a server is appealing, but the overheads of communication can easily mitigate the benefits. Ideally, a task described with one input language can be offloaded to a number of heterogeneous computing platforms. Our article published in The International Journal of High Performance Computing Applications describes how Pocl-R allows low-latency, robust offloading of OpenCL programs over networks. The article is available <a href="https://doi.org/10.1177/10943420251369350">here</a>.
<p align="center">
<img src="img/pocl-r_extension.jpg" border="0"
alt="PoCL-R stack" title="PoCL-R stack" width="500px" />
</p>
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July 7th, 2025: New <a href="publications.html">publication</a> added</div>
<p>
Population ageing is a global societal challenge. The increasing proportion of elderly people of the population comes with increases in healthcare costs. <i>Smart-health cyber-physical (CPS)</i> systems are an approach to alleviate these costs. In collaboration with University of Granada, we propose a framework for monitoring and producing alarms in the context of indoor ambient assisted living for the elderly. The article is titled "<i>Efficient reconfigurable system for home monitoring of the elderly via action recognition</i>" and is available (<a href="https://doi.org/10.1016/j.engappai.2025.111383">here</a>).
</p>
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<div class="news-headline"> June 2nd, 2025: Two new <a href="publications.html">publications</a> and two masters theses added</div>
<ul>
<li>
Jan Solanti, Pekka Jääskeläinen:<br />
<span class='paperTitle'>"Latency Reduction Potential of Server-Side Command Buffers in OpenCL-Based Edge Offloading"</span>,<br />
in in the 13th International Workshop on OpenCL and SYCL (IWOCL), Apr. 2025 (<a href="https://doi.org/10.1145/3731125.3731129">download</a>).
</li>
<li>
Jakub Žádník, Robin Bijl and Jan Solanti, Erno Joensuu, Markku Mäkitalo and Pekka Jääskeläinen:<br />
<span class='paperTitle'>"Open Software Stack for Compression-Aware Adaptive Edge Offloading"</span>,<br />
in in IEEE Wireless Communications and Networking Conference (WCNC), Mar. 2025 (<a href="https://ieeexplore.ieee.org/document/10978312">download</a>).
</li>
<li>
Antti Hahka: <br />
<div class="new-publication">"Physical Safety in Wireless Edge Offloading of Control Decisions: A case study using a nano-drone"</div> (2024) (<a href="https://trepo.tuni.fi/handle/10024/161578">link</a>)
</li>
<li>
Yashvardhan Agarwal: <br />
<div class="new-publication">"Dynamic Device Management and Automatic Network Resource Discovery in OpenCL for Multi-Access Edge Computing"</div> (2024) (<a href="https://research.tue.nl/en/studentTheses/dynamic-device-management-and-automatic-network-resource-discover">link</a>)
</li>
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Apr 29th, 2025: Server side command buffers for efficient OpenCL offloading at IWOCL '25 </div>
<p>
Our doctoral researcher Jan Solanti presented the paper <a href="https://doi.org/10.1145/3731125.3731129">"Latency Reduction Potential of Server-Side Command Buffers in OpenCL-Based Edge Offloading"</a> at IWOCL '25. Command buffers provide applications with a simple way to reduce API overhead from identically repeated workloads, as well as a natural point for OpenCL runtimes to perform optimizations and e.g. submit commands as a batch.
We demonstrate this utility of command buffers with a server-side implementation of command buffers in PoCL-Remote, which will be available in the upcoming <a href="http://portablecl.org/docs/html/notes_7_0.html">PoCL</a> 7.0 release.
</p>
<p align="center">
<img src="img/jan_iwocl_2025.jpg" border="0"
alt="Jan at IWOCL 2025" title="Jan at IWOCL 2025" width="500px" />
</p>
You can watch the presentation below:
<div class="youtube-player" data-id="wWV9dKt0DDU"></div>
</div>
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<div class="news-headline">
Mar 24th, 2025: CPC participates in the DARE project </div>
<p>
The DARE project aims to advance European sovereignty in high-performance computing (HPC). The project designs and develops a general-purpose processor targeted to run major HPC workloads as well as two accelerators: A vector accelerator and an AI processing unit. On the hardware side, CPC is participating in DARE by researching coherent caches in the context of HPC. An efficient memory hierarchy is critical for the manycore processors used in HPC systems as providing data and enabling smooth synchronization can be become a bottleneck for performance. CPC also participates in developing a heterogeneous parallel computing software stack based on <a href="https://portablecl.org/">PoCL</a>, <a href="https://github.com/CHIP-SPV/chipStar">ChipStar</a> and <a href="https://www.khronos.org/sycl/">SYCL</a> with GROMACS as the optimized example HPC application. The project kickoff meeting was held on 10-11 March 2025 in Barcelona, where we were happy to meet great minds from both the academia and industry!<br>
Links:
<ul>
<li>Home page of the DARE project: <a href="https://dare-riscv.eu/home/">https://dare-riscv.eu/home/</a></li>
<li>An article in The Next Platform: <a href="https://www.nextplatform.com/2025/03/10/europe-takes-another-whack-at-homegrown-compute-engines/">"Europe Takes Another Whack at Homegrown Compute Engines"</a></li>
</ul>
</p>
<p align="center">
<img src="img/DARE_group_photo_resized.jpg" border="0"
alt="DARE kickoff group photo" title="DARE kickoff group photo" width="500px" />
</p>
</div>
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(<a href="old_news.html">older news here</a>)
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