From 8cb28826423bb24e35de208512b0593b3b9a94ee Mon Sep 17 00:00:00 2001 From: iso9660 Date: Thu, 14 Dec 2023 10:16:07 +0100 Subject: [PATCH 1/5] Reworked pwm modes to use 24hkz mode at lower throttle and 96khz mode at higher throttle --- src/Modules/Isrs.asm | 177 +++++++++++++++++++++------------------ src/Modules/Settings.asm | 30 +++---- 2 files changed, 109 insertions(+), 98 deletions(-) diff --git a/src/Modules/Isrs.asm b/src/Modules/Isrs.asm index 9ad0e8b..5385cf8 100644 --- a/src/Modules/Isrs.asm +++ b/src/Modules/Isrs.asm @@ -372,28 +372,39 @@ t1_int_dynamic_pwm: ; Dynamic PWM mov A, Temp2 - ; Choose between 96khz and 48khz - clr C - subb A, Throttle_96to48_Threshold - jc t1_int_run_96khz - ; Choose between 48khz and 24khz clr C subb A, Throttle_48to24_Threshold + jc t1_int_run_24khz + + ; Choose between 96khz and 48khz + clr C + subb A, Throttle_96to48_Threshold jc t1_int_run_48khz IF PWM_CENTERED == 0 ; Edge aligned PWM -t1_int_run_24khz: +t1_int_run_96khz: ; Scale pwm resolution and invert (duty cycle is defined inversely) - ; No deadtime and 24khz + ; Deadtime and 96khz + mov B, Temp5 + mov A, Temp4 + mov C, B.0 + rrc A + mov C, B.1 + rrc A + cpl A + mov Temp2, A mov A, Temp5 + rr A + rr A cpl A - anl A, #7 + anl A, #1 mov Temp3, A - mov A, Temp4 - cpl A + + ; Set PCA to work at 96khz (9bit pwm) + mov PCA0PWM, #81h mov Temp2, A ; Set PCA to work at 24khz (11bit pwm) @@ -418,26 +429,15 @@ t1_int_run_48khz: mov PCA0PWM, #82h jmp t1_int_set_pwm -t1_int_run_96khz: +t1_int_run_24khz: ; Scale pwm resolution and invert (duty cycle is defined inversely) - ; Deadtime and 96khz - mov B, Temp5 - mov A, Temp4 - mov C, B.0 - rrc A - mov C, B.1 - rrc A - cpl A - mov Temp2, A + ; No deadtime and 24khz mov A, Temp5 - rr A - rr A cpl A - anl A, #1 + anl A, #7 mov Temp3, A - - ; Set PCA to work at 96khz (9bit pwm) - mov PCA0PWM, #81h + mov A, Temp4 + cpl A t1_int_set_pwm: ; Set PWM registers @@ -449,24 +449,15 @@ t1_int_set_pwm: ELSE ; Center aligned PWM -t1_int_run_24khz: +t1_int_run_96khz: ; Scale pwm resolution and invert (duty cycle is defined inversely) - ; Deadtime and 24khz - clr C - mov A, Temp5 - rrc A - cpl A - anl A, #3 - mov Temp3, A - mov A, Temp4 - rrc A + ; Deadtime and 96khz + mov A, Temp2 ; Temp2 already 8-bit cpl A mov Temp2, A + mov Temp3, #0 - ; Set PCA to work at 24khz (10bit pwm) - mov PCA0PWM, #82h - - ; Subtract dead time from normal pwm and store as damping PWM + ; Substract dead time from normal pwm and store as damping PWM ; Damping PWM duty cycle will be higher because numbers are inverted clr C mov A, Temp2 ; Skew damping FET timing @@ -479,24 +470,37 @@ ENDIF mov A, Temp3 subb A, #0 mov Temp5, A - jnc t1_int_max_braking_set_24khz + jnc t1_int_max_braking_set_96khz clr A ; Set to minimum value mov Temp4, A mov Temp5, A - jmp t1_int_set_pwm ; Max braking is already zero - branch + sjmp t1_int_set_pwm_96khz ; Max braking is already zero - branch -t1_int_max_braking_set_24khz: +t1_int_max_braking_set_96khz: clr C mov A, Temp4 - subb A, Pwm_Braking24_L + subb A, Pwm_Braking96_L mov A, Temp5 - subb A, Pwm_Braking24_H ; Is braking pwm more than maximum allowed braking? - jc t1_int_set_pwm ; Yes - branch + subb A, Pwm_Braking96_H ; Is braking pwm more than maximum allowed braking? + jc t1_int_set_pwm_96khz ; Yes - branch - mov Temp4, Pwm_Braking24_L ; No - set desired braking instead - mov Temp5, Pwm_Braking24_H - jmp t1_int_set_pwm + mov Temp4, Pwm_Braking96_L ; No - set desired braking instead + mov Temp5, Pwm_Braking96_H + +t1_int_set_pwm_96khz: +; Set PWM registers +; NOTE: Interrupts are not explicitly disabled. Assume higher priority +; interrupts (Int0, Timer0) to be disabled at this point. + ; Set PCA to work at 96khz (8bit pwm) + mov PCA0PWM, #80h + + ; Set power pwm auto-reload registers + Set_Power_Pwm_Reg_H Temp2 + + ; Set damp pwm auto-reload registers + Set_Damp_Pwm_Reg_H Temp4 + jmp t1_int_prepare_telemetry t1_int_run_48khz: ; Scale pwm resolution and invert (duty cycle is defined inversely) @@ -516,10 +520,7 @@ t1_int_run_48khz: anl A, #1 mov Temp3, A - ; Set PCA to work at 48khz (9bit pwm) - mov PCA0PWM, #81h - - ; Subtract dead time from normal pwm and store as damping PWM + ; Substract dead time from normal pwm and store as damping PWM ; Damping PWM duty cycle will be higher because numbers are inverted clr C mov A, Temp2 ; Skew damping FET timing @@ -537,7 +538,7 @@ ENDIF clr A ; Set to minimum value mov Temp4, A mov Temp5, A - sjmp t1_int_set_pwm ; Max braking is already zero - branch + sjmp t1_int_set_pwm_48khz ; Max braking is already zero - branch t1_int_max_braking_set_48khz: clr C @@ -545,24 +546,42 @@ t1_int_max_braking_set_48khz: subb A, Pwm_Braking48_L mov A, Temp5 subb A, Pwm_Braking48_H ; Is braking pwm more than maximum allowed braking? - jc t1_int_set_pwm ; Yes - branch + jc t1_int_set_pwm_48khz ; Yes - branch mov Temp4, Pwm_Braking48_L ; No - set desired braking instead mov Temp5, Pwm_Braking48_H - jmp t1_int_set_pwm -t1_int_run_96khz: +t1_int_set_pwm_48khz: +; Set PWM registers +; NOTE: Interrupts are not explicitly disabled. Assume higher priority +; interrupts (Int0, Timer0) to be disabled at this point. + ; Set PCA to work at 48khz (9bit pwm) + mov PCA0PWM, #81h + + ; Set power pwm auto-reload registers + Set_Power_Pwm_Reg_L Temp2 + Set_Power_Pwm_Reg_H Temp3 + + ; Set damp pwm auto-reload registers + Set_Damp_Pwm_Reg_L Temp4 + Set_Damp_Pwm_Reg_H Temp5 + jmp t1_int_prepare_telemetry + +t1_int_run_24khz: ; Scale pwm resolution and invert (duty cycle is defined inversely) - ; Deadtime and 96khz - mov A, Temp2 ; Temp2 already 8-bit + ; Deadtime and 24khz + clr C + mov A, Temp5 + rrc A + cpl A + anl A, #3 + mov Temp3, A + mov A, Temp4 + rrc A cpl A mov Temp2, A - mov Temp3, #0 - - ; Set PCA to work at 96khz (8bit pwm) - mov PCA0PWM, #80h - ; Subtract dead time from normal pwm and store as damping PWM + ; Substract dead time from normal pwm and store as damping PWM ; Damping PWM duty cycle will be higher because numbers are inverted clr C mov A, Temp2 ; Skew damping FET timing @@ -575,39 +594,31 @@ ENDIF mov A, Temp3 subb A, #0 mov Temp5, A - jnc t1_int_max_braking_set_96khz + jnc t1_int_max_braking_set_24khz clr A ; Set to minimum value mov Temp4, A mov Temp5, A - sjmp t1_int_set_pwm_96khz ; Max braking is already zero - branch + jmp t1_int_set_pwm_24khz ; Max braking is already zero - branch -t1_int_max_braking_set_96khz: +t1_int_max_braking_set_24khz: clr C mov A, Temp4 - subb A, Pwm_Braking96_L + subb A, Pwm_Braking24_L mov A, Temp5 - subb A, Pwm_Braking96_H ; Is braking pwm more than maximum allowed braking? - jc t1_int_set_pwm_96khz ; Yes - branch + subb A, Pwm_Braking24_H ; Is braking pwm more than maximum allowed braking? + jc t1_int_set_pwm_24khz ; Yes - branch - mov Temp4, Pwm_Braking96_L ; No - set desired braking instead - mov Temp5, Pwm_Braking96_H + mov Temp4, Pwm_Braking24_L ; No - set desired braking instead + mov Temp5, Pwm_Braking24_H -t1_int_set_pwm_96khz: +t1_int_set_pwm_24khz: ; Set PWM registers ; NOTE: Interrupts are not explicitly disabled. Assume higher priority ; interrupts (Int0, Timer0) to be disabled at this point. - ; Set power pwm auto-reload registers - Set_Power_Pwm_Reg_H Temp2 - - ; Set damp pwm auto-reload registers - Set_Damp_Pwm_Reg_H Temp4 - jmp t1_int_prepare_telemetry + ; Set PCA to work at 24khz (10bit pwm) + mov PCA0PWM, #82h -t1_int_set_pwm: -; Set PWM registers -; NOTE: Interrupts are not explicitly disabled. Assume higher priority -; interrupts (Int0, Timer0) to be disabled at this point. ; Set power pwm auto-reload registers Set_Power_Pwm_Reg_L Temp2 Set_Power_Pwm_Reg_H Temp3 diff --git a/src/Modules/Settings.asm b/src/Modules/Settings.asm index 3f28701..d00910a 100644 --- a/src/Modules/Settings.asm +++ b/src/Modules/Settings.asm @@ -211,44 +211,44 @@ decode_throttle_threshold: ; Check 24khz pwm frequency cjne A, #24, decode_throttle_not_24 - mov Throttle_96to48_Threshold, #0 - mov Throttle_48to24_Threshold, #0 + mov Throttle_96to48_Threshold, #255 + mov Throttle_48to24_Threshold, #255 jmp decode_end decode_throttle_not_24: ; Check 48khz pwm frequency cjne A, #48, decode_throttle_not_48 - mov Throttle_96to48_Threshold, #0 - mov Throttle_48to24_Threshold, #255 + mov Throttle_96to48_Threshold, #255 + mov Throttle_48to24_Threshold, #0 jmp decode_end decode_throttle_not_48: ; Check 96khz pwm frequency cjne A, #96, decode_throttle_not_96 - mov Throttle_96to48_Threshold, #255 - mov Throttle_48to24_Threshold, #255 + mov Throttle_96to48_Threshold, #0 + mov Throttle_48to24_Threshold, #0 jmp decode_end decode_throttle_not_96: ; Dynamic pwm frequency - ; Load programmed throttle threshold into Throttle_96to48_Threshold - mov Temp1, #Pgm_96to48_Threshold - mov Throttle_96to48_Threshold, @Temp1 - ; Load programmed throttle threshold into Throttle_48to24_Threshold mov Temp1, #Pgm_48to24_Threshold mov Throttle_48to24_Threshold, @Temp1 - ; Sanitize Throttle_48to24_Threshold + ; Load programmed throttle threshold into Throttle_96to48_Threshold + mov Temp1, #Pgm_96to48_Threshold + mov Throttle_96to48_Threshold, @Temp1 + + ; Sanitize Throttle_96to48_Threshold clr C - mov A, Throttle_48to24_Threshold - subb A, Throttle_96to48_Threshold + mov A, Throttle_96to48_Threshold + subb A, Throttle_48to24_Threshold jnc decode_throttle_not_96_end clr A decode_throttle_not_96_end: - ; Update Throttle_48to24_Threshold - mov Throttle_48to24_Threshold, A + ; Update Throttle_96to48_Threshold + mov Throttle_96to48_Threshold, A decode_end: ret From 6831683f6d5db9e03816df7a3f411802f6f9c0d2 Mon Sep 17 00:00:00 2001 From: iso9660 Date: Mon, 18 Dec 2023 18:24:11 +0100 Subject: [PATCH 2/5] Do not load braking strength setting when using edge aligned PWM --- src/Modules/Settings.asm | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/Modules/Settings.asm b/src/Modules/Settings.asm index d00910a..c9e04ed 100644 --- a/src/Modules/Settings.asm +++ b/src/Modules/Settings.asm @@ -166,12 +166,12 @@ decode_temp_done: mov Temp1, #Pgm_Beep_Strength ; Read programmed beep strength setting mov Beep_Strength, @Temp1 ; Set beep strength - ; Read programmed braking strength setting - mov Temp1, #Pgm_Braking_Strength - ; Scale braking strength to pwm resolution ; Only for center aligned pwm modes (edge aligned pwm insert deadtime by hw) IF PWM_CENTERED == 1 + ; Read programmed braking strength setting + mov Temp1, #Pgm_Braking_Strength + ; Deadtime & 24khz (10bit pwm) mov A, @Temp1 rl A From 092d90f83d71326d9d047b2dbe9af3f6e13517a8 Mon Sep 17 00:00:00 2001 From: damosvil Date: Tue, 19 Dec 2023 11:39:52 +0100 Subject: [PATCH 3/5] Optimized 96khz pwm mode --- src/Bluejay.asm | 1 - src/Modules/Isrs.asm | 13 ++----------- src/Modules/Settings.asm | 1 - 3 files changed, 2 insertions(+), 13 deletions(-) diff --git a/src/Bluejay.asm b/src/Bluejay.asm index 6428386..30680e6 100644 --- a/src/Bluejay.asm +++ b/src/Bluejay.asm @@ -244,7 +244,6 @@ Pwm_Braking24_H: DS 1 ; Max Braking @24khz pwm (hi byte) Pwm_Braking48_L: DS 1 ; Max Braking @48khz pwm (lo byte) Pwm_Braking48_H: DS 1 ; Max Braking @48khz pwm (hi byte) Pwm_Braking96_L: DS 1 ; Max Braking @96khz pwm (lo byte) -Pwm_Braking96_H: DS 1 ; Max Braking @96khz pwm (hi byte) Temp_Prot_Limit: DS 1 ; Temperature protection limit Temp_Pwm_Level_Setpoint: DS 1 ; PWM level setpoint Beep_Strength: DS 1 ; Strength of beeps diff --git a/src/Modules/Isrs.asm b/src/Modules/Isrs.asm index 5385cf8..f7b199b 100644 --- a/src/Modules/Isrs.asm +++ b/src/Modules/Isrs.asm @@ -455,7 +455,6 @@ t1_int_run_96khz: mov A, Temp2 ; Temp2 already 8-bit cpl A mov Temp2, A - mov Temp3, #0 ; Substract dead time from normal pwm and store as damping PWM ; Damping PWM duty cycle will be higher because numbers are inverted @@ -467,26 +466,18 @@ ELSE subb A, #(DEADTIME) ENDIF mov Temp4, A - mov A, Temp3 - subb A, #0 - mov Temp5, A jnc t1_int_max_braking_set_96khz - clr A ; Set to minimum value - mov Temp4, A - mov Temp5, A + mov Temp4, #0 ; Set to minimum value sjmp t1_int_set_pwm_96khz ; Max braking is already zero - branch t1_int_max_braking_set_96khz: clr C mov A, Temp4 - subb A, Pwm_Braking96_L - mov A, Temp5 - subb A, Pwm_Braking96_H ; Is braking pwm more than maximum allowed braking? + subb A, Pwm_Braking96_L ; Is braking pwm more than maximum allowed braking? jc t1_int_set_pwm_96khz ; Yes - branch mov Temp4, Pwm_Braking96_L ; No - set desired braking instead - mov Temp5, Pwm_Braking96_H t1_int_set_pwm_96khz: ; Set PWM registers diff --git a/src/Modules/Settings.asm b/src/Modules/Settings.asm index c9e04ed..e3e39ff 100644 --- a/src/Modules/Settings.asm +++ b/src/Modules/Settings.asm @@ -195,7 +195,6 @@ IF PWM_CENTERED == 1 ; Deadtime & 96khz (8bit pwm) mov A, @Temp1 - mov Pwm_Braking96_H, #0 mov Pwm_Braking96_L, A cjne @Temp1, #0FFh, decode_throttle_threshold From 59f02573498d0d8e8bf898d98633f984fe26b174 Mon Sep 17 00:00:00 2001 From: damosvil Date: Tue, 19 Dec 2023 12:37:37 +0100 Subject: [PATCH 4/5] Dynamic pwm threshold defaults set to the correct values --- src/Modules/Isrs.asm | 2 +- src/Settings/BluejaySettings.asm | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/Modules/Isrs.asm b/src/Modules/Isrs.asm index f7b199b..27c0f3b 100644 --- a/src/Modules/Isrs.asm +++ b/src/Modules/Isrs.asm @@ -598,7 +598,7 @@ t1_int_max_braking_set_24khz: subb A, Pwm_Braking24_L mov A, Temp5 subb A, Pwm_Braking24_H ; Is braking pwm more than maximum allowed braking? - jc t1_int_set_pwm_24khz ; Yes - branch + jc t1_int_set_pwm_24khz ; Yes - branch mov Temp4, Pwm_Braking24_L ; No - set desired braking instead mov Temp5, Pwm_Braking24_H diff --git a/src/Settings/BluejaySettings.asm b/src/Settings/BluejaySettings.asm index 485796f..11bde3a 100644 --- a/src/Settings/BluejaySettings.asm +++ b/src/Settings/BluejaySettings.asm @@ -49,5 +49,5 @@ DEFAULT_PGM_STARTUP_POWER_MAX EQU 5 ; 0..255 => (1000..2000 Throttle): Maxim DEFAULT_PGM_BRAKING_STRENGTH EQU 255 ; 0..255 => 0..100 % Braking DEFAULT_PGM_SAFETY_ARM EQU 0 ; EDT safety arm is disabled by default -DEFAULT_96to48_THRESHOLD EQU 85 ; About 33% threshold to change between 96 and 48khz -DEFAULT_48to24_THRESHOLD EQU 170 ; About 66% threshold to change between 48 and 24khz +DEFAULT_48to24_THRESHOLD EQU 85 ; About 33% threshold to change between 48 and 24khz +DEFAULT_96to48_THRESHOLD EQU 170 ; About 66% threshold to change between 96 and 48khz From 0301e86c5b55d724259f69cf6ada9d881f256399 Mon Sep 17 00:00:00 2001 From: damosvil Date: Wed, 20 Dec 2023 08:54:11 +0100 Subject: [PATCH 5/5] Relaxed 96khz pwm mode optimization --- src/Modules/Isrs.asm | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/Modules/Isrs.asm b/src/Modules/Isrs.asm index 27c0f3b..34deabd 100644 --- a/src/Modules/Isrs.asm +++ b/src/Modules/Isrs.asm @@ -455,6 +455,7 @@ t1_int_run_96khz: mov A, Temp2 ; Temp2 already 8-bit cpl A mov Temp2, A + mov Temp3, #0 ; Substract dead time from normal pwm and store as damping PWM ; Damping PWM duty cycle will be higher because numbers are inverted @@ -466,18 +467,26 @@ ELSE subb A, #(DEADTIME) ENDIF mov Temp4, A + mov A, Temp3 + subb A, #0 + mov Temp5, A jnc t1_int_max_braking_set_96khz - mov Temp4, #0 ; Set to minimum value + clr A ; Set to minimum value + mov Temp4, A + mov Temp5, A sjmp t1_int_set_pwm_96khz ; Max braking is already zero - branch t1_int_max_braking_set_96khz: clr C mov A, Temp4 - subb A, Pwm_Braking96_L ; Is braking pwm more than maximum allowed braking? + subb A, Pwm_Braking96_L + mov A, Temp5 + subb A, #0 ; Is braking pwm more than maximum allowed braking? (Pwm_Braking96_H is 0, 8-bit) jc t1_int_set_pwm_96khz ; Yes - branch mov Temp4, Pwm_Braking96_L ; No - set desired braking instead + mov Temp5, #0 ; Pwm_Braking96_H is 0, 8-bit t1_int_set_pwm_96khz: ; Set PWM registers